M. Rack , M. Nabet , Y. Bendou , M. Vanbrabant , M. Moulin , Q. Courte , S. Cremer , A. Cathelin , D. Lederer , J.-P. Raskin
{"title":"28 nm FD-SOI中PN钝化的低损耗硅衬底","authors":"M. Rack , M. Nabet , Y. Bendou , M. Vanbrabant , M. Moulin , Q. Courte , S. Cremer , A. Cathelin , D. Lederer , J.-P. Raskin","doi":"10.1016/j.sse.2025.109174","DOIUrl":null,"url":null,"abstract":"<div><div>In this work, the 28 nm FD-SOI technology from ST Microelectronics was run for the first time on high-resistivity wafer samples. The gain in RF performance through the use of high-resistivity bulk is characterized in terms of losses, effective resistivity (ρ<sub>eff</sub>) and generated harmonics through on-wafer measurements of coplanar waveguides (CPW). Beyond the use of a high-resistivity bulk, special care was taken to ensure a state of high-resistivity at the silicon/oxide interface. This was achieved through the PN junction interface passivation solution, implemented locally on the wafer at the foundry level, below passive RF devices. A study was performed on the dose and energy parameters of these implants to achieve optimal RF performance and giving insight into the PN design.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109174"},"PeriodicalIF":1.4000,"publicationDate":"2025-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low-loss silicon substrates with PN passivation in 28 nm FD-SOI\",\"authors\":\"M. Rack , M. Nabet , Y. Bendou , M. Vanbrabant , M. Moulin , Q. Courte , S. Cremer , A. Cathelin , D. Lederer , J.-P. Raskin\",\"doi\":\"10.1016/j.sse.2025.109174\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>In this work, the 28 nm FD-SOI technology from ST Microelectronics was run for the first time on high-resistivity wafer samples. The gain in RF performance through the use of high-resistivity bulk is characterized in terms of losses, effective resistivity (ρ<sub>eff</sub>) and generated harmonics through on-wafer measurements of coplanar waveguides (CPW). Beyond the use of a high-resistivity bulk, special care was taken to ensure a state of high-resistivity at the silicon/oxide interface. This was achieved through the PN junction interface passivation solution, implemented locally on the wafer at the foundry level, below passive RF devices. A study was performed on the dose and energy parameters of these implants to achieve optimal RF performance and giving insight into the PN design.</div></div>\",\"PeriodicalId\":21909,\"journal\":{\"name\":\"Solid-state Electronics\",\"volume\":\"229 \",\"pages\":\"Article 109174\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid-state Electronics\",\"FirstCategoryId\":\"101\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0038110125001194\",\"RegionNum\":4,\"RegionCategory\":\"物理与天体物理\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125001194","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Low-loss silicon substrates with PN passivation in 28 nm FD-SOI
In this work, the 28 nm FD-SOI technology from ST Microelectronics was run for the first time on high-resistivity wafer samples. The gain in RF performance through the use of high-resistivity bulk is characterized in terms of losses, effective resistivity (ρeff) and generated harmonics through on-wafer measurements of coplanar waveguides (CPW). Beyond the use of a high-resistivity bulk, special care was taken to ensure a state of high-resistivity at the silicon/oxide interface. This was achieved through the PN junction interface passivation solution, implemented locally on the wafer at the foundry level, below passive RF devices. A study was performed on the dose and energy parameters of these implants to achieve optimal RF performance and giving insight into the PN design.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.