C.A.B. Mori , P.H. Duarte , R.C. Rangel , P.G.D. Agopian , J.A. Martino
{"title":"The Dual-Technology FET: nMOS/pTFET in the same device","authors":"C.A.B. Mori , P.H. Duarte , R.C. Rangel , P.G.D. Agopian , J.A. Martino","doi":"10.1016/j.sse.2025.109177","DOIUrl":null,"url":null,"abstract":"<div><div>This work presents for the first time the experimental results of a Dual-Technology FET (DT-FET). DT-FET is a SOI transistor capable of operating either as an n-type MOSFET (nMOS) or a p-type Tunnel-FET (pTFET), depending on the back gate bias and the source/drain bias conditions. It is an extension of the <sup>BE</sup>SOI MOSFET, with the addition of N + at the drain or source region, which results in different physics of operation depending on back the gate bias. For a positive back gate bias the device behaves as an nMOS, while for a negative back gate bias it behaves as a pTFET. The results were compared with 2D simulations, showing that the overall trends are similar.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109177"},"PeriodicalIF":1.4000,"publicationDate":"2025-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125001224","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This work presents for the first time the experimental results of a Dual-Technology FET (DT-FET). DT-FET is a SOI transistor capable of operating either as an n-type MOSFET (nMOS) or a p-type Tunnel-FET (pTFET), depending on the back gate bias and the source/drain bias conditions. It is an extension of the BESOI MOSFET, with the addition of N + at the drain or source region, which results in different physics of operation depending on back the gate bias. For a positive back gate bias the device behaves as an nMOS, while for a negative back gate bias it behaves as a pTFET. The results were compared with 2D simulations, showing that the overall trends are similar.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.