Eui Joong Shin, Jaejoong Jeong, Gyusoup Lee, Seongho Kim, Byung Jin Cho
{"title":"Suppression of de-trapping by remanent polarization in dual-mechanism flash memory","authors":"Eui Joong Shin, Jaejoong Jeong, Gyusoup Lee, Seongho Kim, Byung Jin Cho","doi":"10.1016/j.sse.2024.109049","DOIUrl":"10.1016/j.sse.2024.109049","url":null,"abstract":"<div><div>Recently, a dual-mechanism Flash memory cell that utilizes both charge trapping and polarization switching as the memory mechanism was proposed <span><span>[1]</span></span>. In this work, the data retention characteristics of the dual-mechanism memory are extensively studied. Lifetime and activation energy analyses show that the remanent polarization in the blocking layer of the dual-mechanism memory suppresses the de-trapping of electrons in the charge trap layer. A quantitative analysis of the trapped charge and remanent polarization revealed that the electrons can be stored in a potential well created by the remanent polarization, which effectively improves the retention characteristics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109049"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulation and experimental Demonstration on A retrograde drift LDMOS","authors":"Shaoxin Yu , Rongsheng Chen , Weiheng Shao , Xiaoyan Zhao , Zheng Chen , Weizhong Shan , Jenhao Cheng","doi":"10.1016/j.sse.2024.109050","DOIUrl":"10.1016/j.sse.2024.109050","url":null,"abstract":"<div><div>In this article, an RD (Retrograde drift) LDMOS (Lateral double diffused metal oxide semiconductor) device is introduced. The drift region in this proposed device is trapezoidal in shape and gradually decreases from top to bottom in doping concentration, called “retrograde drift.” Simulations indicate that this RD device has an 11.7% lower electric field peak value, 6.2% lower potential under the poly gate, 32.1% higher current width in the drift region, and 10.5% lower impact gen rate at the corner of FP (Field plate) as well. A series of devices have been fabricated using a photoresist treatment process. Compared with the conventional BD (box-shape drift) device, the RD device’s <span><math><mrow><mi>BV</mi></mrow></math></span>(Breakdown voltage)-<span><math><msub><mi>R</mi><mrow><mi>on</mi><mo>,</mo><mi>s</mi><mi>p</mi></mrow></msub></math></span> (on-resistance) FOM (Figure of merit) performance is improved by 30.9%, and the <span><math><msub><mi>Q</mi><mrow><mi>gd</mi></mrow></msub></math></span>(Gate-drain charge)-<span><math><msub><mi>R</mi><mrow><mi>on</mi><mo>,</mo><mi>s</mi><mi>p</mi></mrow></msub></math></span> FOM character is improved by 42.1%. Moreover, the RD device owns better HCI (Hot carrier injection) performance on both <span><math><msub><mi>R</mi><mrow><mi>on</mi><mo>,</mo><mi>s</mi><mi>p</mi></mrow></msub></math></span> degradation and <span><math><msub><mi>V</mi><mi>T</mi></msub></math></span> (Threshold voltage) degradation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109050"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhizhao Ma , Hao Su , Yuhuan Lin , Shenghua Zhou , Feichi Zhou , Xiaoguang Liu , Longyang Lin , Yida Li , Kai Chen
{"title":"Comprehensive analysis of MOSFET threshold voltage extraction method considering DIBL effect from 300 K down to 10 K","authors":"Zhizhao Ma , Hao Su , Yuhuan Lin , Shenghua Zhou , Feichi Zhou , Xiaoguang Liu , Longyang Lin , Yida Li , Kai Chen","doi":"10.1016/j.sse.2024.109045","DOIUrl":"10.1016/j.sse.2024.109045","url":null,"abstract":"<div><div>It is well known that different threshold voltage <em>(V<sub>th</sub>)</em> extraction methods exhibit inconsistencies with respect to different drain voltage (<em>V<sub>d</sub></em>). This inconsistency becomes disruptive when temperature is considered for cryogenic applications such as quantum computing. This investigation examines various <em>V<sub>th</sub></em> extraction methods from room down to cryogenic temperatures, with a particular emphasis on how different <em>V<sub>d</sub></em> values combined with extraction methods behave as temperature decreases. For the first time, we find that the square root <em>I<sub>d</sub></em> method maintains consistency regardless of <em>V<sub>d</sub></em>, from 300 K all the way down to 10 K is identified. This provides a good insight into how the Drain-Induced Barrier Lowering (DIBL) effect changes with temperature, and positions the square root <em>I<sub>d</sub></em> method as a reliable tool for <em>V<sub>th</sub></em> extraction in cryogenic temperature.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109045"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bo Liu , Yong-Bo Su , Ren-Jie Liu , Zhi Jin , Chao Zhang , Ying-Hui Zhong
{"title":"Equivalence of proton-induced displacement damage in InP-based HEMT","authors":"Bo Liu , Yong-Bo Su , Ren-Jie Liu , Zhi Jin , Chao Zhang , Ying-Hui Zhong","doi":"10.1016/j.sse.2024.109048","DOIUrl":"10.1016/j.sse.2024.109048","url":null,"abstract":"<div><div>Radiation experiments of 560 keV, 2 MeV, and 10 MeV proton have been performed on InP-based High Electron Mobility Transistors (HEMTs), the damage mechanisms and damage equivalence are systematically studied. The irradiated devices have exhibited the reduction of transconductance, the positive shift of threshold voltage, and the reduction in drain-source current. Nonionizing energy loss (NIEL) was calculated to investigate the relationship between the degradation of the device and proton energy, but the damage factors of the devices do not exhibit a perfect linear relationship with NIEL across all the energies. The deviation mainly lies in the stopping power of the target material for incident protons. An improved NIEL calculation method is proposed based on Geant4 simulation software, which eliminates the influence of stopping power. And thus, the equivalence of displacement damage in InP-based HEMTs has been constructed among 560 keV, 2 MeV, and 10 MeV proton irradiation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109048"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Guangxin Guo, Zhengguang Tang, Zhenhai Cui, Cong Li, Hailong You
{"title":"GatedNN: An accurate deep learning-based parameter extraction for BSIM-CMG","authors":"Guangxin Guo, Zhengguang Tang, Zhenhai Cui, Cong Li, Hailong You","doi":"10.1016/j.sse.2024.109044","DOIUrl":"10.1016/j.sse.2024.109044","url":null,"abstract":"<div><div>An enhanced deep learning (DL) -based parameter extraction method for transistor compact models, named GatedNN, is introduced. GatedNN achieves significant accuracy improvements over existing DL-based parameter extraction techniques. The innovation lies in incorporating neural network (NN) with gating mechanism and compact model-aware techniques: model parameter importance analysis and model quality check. The GatedNN uses gates to resolve optimization conflicts among model parameters by controlling gradient descent during training. The importance analysis focuses on optimizing more crucial parameters that contribute to the current curve. The model quality check cleans the training data fed to the GatedNN and ensures the robustness of the NN output. Evaluated on the BSIM-CMG model with measured FinFET data, the proposed approach demonstrates a substantial 69% error reduction compared to recently DL-based parameter extractor. Furthermore, the scalability and mathematical robustness of the generated model are tested. The proposed GatedNN also provides insights into model parameters and device characteristics, aiding in understanding and adjusting for desired characteristics. We believe the developed method can advance the development of DL-based parameter extraction.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109044"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhanced threshold voltage tuning in FD-SOI MOSFET with ferroelectric buried oxide","authors":"Sorin Cristoloveanu , Etienne Nowak , Justine Barbot , Laurent Grenouillet , Ionut Radu","doi":"10.1016/j.sse.2024.109052","DOIUrl":"10.1016/j.sse.2024.109052","url":null,"abstract":"<div><div>A ferroelectric buried oxide is demonstrated to considerably enhance the tunability of the threshold voltage in FD-SOI transistors. The polarization mechanism makes the rate of change of threshold voltage with back-gate voltage increase tremendously from 4–5 % to more than 50 %. Our model and simulations show that with 1 V applied on the ground-plane, the threshold voltage is shifted by half a volt, which dramatically improves power consumption and speed.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109052"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study on electrical performance of AlGaN/GaN high electron mobility transistor based on cap layer design","authors":"Tieying Zhang, Peng Cui, Xin Luo, Siheng Chen, Liu Wang, Jiacheng Dai, Kaifa Qi, Handoko Linewih, Zhaojun Lin, Xiangang Xu, Jisheng Han","doi":"10.1016/j.sse.2024.109051","DOIUrl":"10.1016/j.sse.2024.109051","url":null,"abstract":"<div><div>This study investigates the impact of different cap layers on the electrical properties of AlGaN/GaN high electron mobility transistors (HEMTs). By comparing the fabricated AlGaN/GaN HEMTs with GaN and AlN cap layers, it was found that AlN cap layer increases the two-dimensional electron gas (2DEG) density due to its superior passivation and polarization effects, yielding a higher saturation current and boosting breakdown voltage from 615 V (GaN) to 895 V (AlN). Sentaurus TCAD simulations confirm these findings, showing a deeper energy band triangular potential well in AlN-capped HEMTs, leading to a 2DEG electron density of 1.19 × 10<sup>13</sup> cm<sup>−2</sup>, compared to 0.93 × 10<sup>13</sup> cm<sup>−2</sup> for GaN-capped HEMTs. The larger energy band gap of AlN cap layer provides a more effective potential barrier, reducing electric field intensity and increasing breakdown voltage. Additionally, the novel AlN-AlGaN-GaN and GaN-AlGaN-AlN graded cap layers are proposed to further enhance breakdown voltage, reaching up to 1308 V. These graded structures balance the electric field, block electron leakage, and improve electron transfer, providing a significant performance boost. This study underscores the potential of AlN and graded cap layers for future high-performance HEMTs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109051"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu Yan , Weijia Song , Cunhua Dou , Xing Zhao , Shujian Xue , Yong Xu , Binhong Li , Yun Wang , Tianchun Ye , Sorin Cristoloveanu
{"title":"A planar core-shell junctionless transistor compatible with FD-SOI Technology","authors":"Yu Yan , Weijia Song , Cunhua Dou , Xing Zhao , Shujian Xue , Yong Xu , Binhong Li , Yun Wang , Tianchun Ye , Sorin Cristoloveanu","doi":"10.1016/j.sse.2025.109079","DOIUrl":"10.1016/j.sse.2025.109079","url":null,"abstract":"<div><div>A planar version of Core-Shell Junctionless transistor (CS-JL FET), fully compatible with standard FDSOI process, is proposed and documented. An undoped region (shell) is added on top of a heavily doped core that bridges the source and drain terminals. While the fundamental advantages of junctionless (JL) MOSFET are maintained, its demerits are eliminated. The CS-JL FET features normally-off operation, high current drive and excellent mobility. The impact of layer thickness, core doping, back bias and gate length are discussed.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109079"},"PeriodicalIF":1.4,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143280042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}