Solid-state Electronics最新文献_第3页

Investigation on the performance limits of Dirac-source FETs 狄拉克源场效应管性能极限的研究

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-23 DOI: 10.1016/j.sse.2025.109124

Tommaso Ugolini, Elena Gnani

引用次数: 0

Studies on resistive switching mechanisms in RRAM memory structures based on copper (II) oxide 基于氧化铜的RRAM存储器结构中电阻开关机制的研究

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-22 DOI: 10.1016/j.sse.2025.109140

M. Ozga , R. Mroczynski , A. Wolska , M. Klepka , M. Godlewski , B.S. Witkowski

引用次数: 0

Adaptive body biasing technique based digital LDO regulator for transient response improvement 基于自适应体偏置技术的数字LDO调节器改善瞬态响应

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-22 DOI: 10.1016/j.sse.2025.109137

Kartikay Mani Tripathi , Madhav Pathak , Sanjeev Manhas , Anand Bulusu

{"title":"Adaptive body biasing technique based digital LDO regulator for transient response improvement","authors":"Kartikay Mani Tripathi , Madhav Pathak , Sanjeev Manhas , Anand Bulusu","doi":"10.1016/j.sse.2025.109137","DOIUrl":"10.1016/j.sse.2025.109137","url":null,"abstract":"<div><div>This paper introduces an adaptive body biasing (ABB) technique for improving the transient response of the Digital Low-Dropout regulator (DLDO) during events of step increment in the load current demand. The proposed ABB technique detects voltage undershoot and dynamically tunes the body bias of the pMOSFETs in the DLDO’s switching array to reduce its threshold voltage, thereby boosting the current supply to help meet the transient load demand. With an ABB-integrated DLDO, designed and simulated in a 28 nm FDSOI (RVT) process, we achieve a reduction in the peak output voltage undershoot and recovery time by 21.23 % and 41.13 %, respectively, compared to DLDO operation without ABB. To validate our approach in the bulk CMOS process, we also designed the ABB-integrated DLDO in a 180 nm bulk process and reported a reduction in the peak output voltage undershoot and recovery time by 13.69 % and 43.8 %, respectively. The robustness of the design to mismatches and process variations is justified via Monte-Carlo simulations, indicating the reliable performance of the proposed ABB technique in DLDO.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109137"},"PeriodicalIF":1.4,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143879333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal coupling between FD-SOI FETs at cryogenic temperatures FD-SOI场效应管在低温下的热耦合

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-22 DOI: 10.1016/j.sse.2025.109132

Martin Vanbrabant, Jean-Pierre Raskin, Valeriya Kilchytska

引用次数: 0

Analog behavior of forksheet FET at high temperatures 高温下叉片场效应管的模拟行为

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-22 DOI: 10.1016/j.sse.2025.109139

Joao Antonio Martino , Paula Ghedini Der Agopian , Julius Andretti Peixoto Pires de Paula , Romain Ritzenthaler , Hans Mertens , Anabela Veloso , Naoto Horiguchi

{"title":"Analog behavior of forksheet FET at high temperatures","authors":"Joao Antonio Martino , Paula Ghedini Der Agopian , Julius Andretti Peixoto Pires de Paula , Romain Ritzenthaler , Hans Mertens , Anabela Veloso , Naoto Horiguchi","doi":"10.1016/j.sse.2025.109139","DOIUrl":"10.1016/j.sse.2025.109139","url":null,"abstract":"<div><div>This work presents an experimental study of the analog behavior of forksheet FET from room up to 150 °C with channel lengths of 26 and 70 nm. These devices present a Zero Temperature-Coefficient (ZTC) point for a gate voltage around 0,59 V (V<sub>ZTC</sub>) in saturation region. The threshold voltage variation with temperature (dV<sub>T</sub>/dT) is around −0,5mV/<sup>o</sup>C due to the Fermi level decrease. The DIBL increases with temperature but it is kept lower than 51 mV/V in the studied temperature range. The transconductance and output conductance decrease (mainly due the mobility degradation) which results in a good intrinsic voltage gain of around 36 dB at room temperature, showing a slight change (±2dB) in the studied temperature range. The maximum unity gain frequency estimated for L = 26 nm is around 358 GHz in strong inversion regime. The results show that the forksheet FETs present a good performance for analog applications at high temperature, which in addition to the already known savings in footprint area compared to nanosheet technology, are potentially useful for future mixed-signal integrated circuits.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109139"},"PeriodicalIF":1.4,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of multiple MISHEMT conduction channels on its analog behavior 多个MISHEMT传导通道对其模拟性能的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-22 DOI: 10.1016/j.sse.2025.109136

Bruno G. Canales , Bruno C.S. Sanches , Joao A. Martino , Eddy Simoen , Uthayasankaran Peralagu , Nadine Collaert , Paula G.D. Agopian

引用次数: 0

Evaluation of the effective channel length of Junctionless nanowire transistors with different drain bias through the gate capacitance 通过栅极电容评价不同漏极偏压无结纳米线晶体管的有效沟道长度

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-22 DOI: 10.1016/j.sse.2025.109134

Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria

{"title":"Evaluation of the effective channel length of Junctionless nanowire transistors with different drain bias through the gate capacitance","authors":"Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria","doi":"10.1016/j.sse.2025.109134","DOIUrl":"10.1016/j.sse.2025.109134","url":null,"abstract":"<div><div>This paper analyzes through 3D numerical simulations the effective channel length (L<sub>EFF</sub>) of Junctionless Nanowire Transistors (JNT) through the gate capacitance (C<sub>GG</sub>) of the devices for different drain-to-source voltages (V<sub>DS</sub>) and compares the results with a theoretical approach. In this case, there is a phenomenon of intersection through the C<sub>GG</sub> curves for high V<sub>DS</sub> bias (between 0.5 V and 1 V) that indicates the pinch-off regime of the JNTs. The L<sub>EFF</sub> extraction has been done from the extrapolation of the gate capacitance in the pinch-off regime as a function of the device’s channel length (L<sub>MASK</sub>), for different L<sub>MASK</sub> and source and drain lengths (L<sub>SD</sub>) for structures with lateral spacer and different doping concentrations, showing that L<sub>EEF</sub> increases ∼ 6 nm and presents a relationship with V<sub>DS</sub> bias and doping concentration. Finally, one comparison with the theoretical equation was done, showing that the method is a good way to extract or even estimate the effective channel length of the experimental devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109134"},"PeriodicalIF":1.4,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143874712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reactive sputtering deposited α-MoO3 thin films for forming-free resistive random-access memory 反应溅射沉积α-MoO3薄膜用于无形成电阻随机存取存储器

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-18 DOI: 10.1016/j.sse.2025.109130

Zeqi Guo , Xiaoxu Lai , Wenhui Xu , Dan Sun , Chi Chen

{"title":"Reactive sputtering deposited α-MoO3 thin films for forming-free resistive random-access memory","authors":"Zeqi Guo , Xiaoxu Lai , Wenhui Xu , Dan Sun , Chi Chen","doi":"10.1016/j.sse.2025.109130","DOIUrl":"10.1016/j.sse.2025.109130","url":null,"abstract":"<div><div>In this study, α-MoO<sub>3</sub> thin films were prepared on single-side polished (1 0 0) silicon substrates using radio-frequency reactive sputtering. By adjusting the substrate temperature and oxygen proportion, α-MoO<sub>3</sub> thin films with desirable crystal phase and surface morphology were successfully grown. The substrate temperature exceeded 400℃ and the oxygen proportion of 50 % are essential for the deposition of a single-phase polycrystalline α-MoO<sub>3</sub> film with abundant oxygen vacancies. A resistive random-access memory (RRAM) device fabricated by the as-prepared α-MoO<sub>3</sub> film exhibited stable resistive switching characteristics with a forming-free behavior, achieving set/reset voltages below 0.3 V, a cycling durability over 250 cycles and an ON/OFF ratio of 10<sup>2</sup>. Furthermore, I-V curve fitting analysis revealed a trap-controlled electron conduction mechanism in the RRAM device, where the high-resistance state exhibited a space-charge-limited current (SCLC) conduction mode. This study demonstrates the significant potential of radio-frequency reactive sputtering for fabricating functional materials for the application of electronic devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109130"},"PeriodicalIF":1.4,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143859921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DFT study of adsorption density of gas molecules in 2D materials 二维材料中气体分子吸附密度的DFT研究

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-18 DOI: 10.1016/j.sse.2025.109116

R. Ortega, L. Donetti, C. Navarro, C. Márquez, F. Gámiz

引用次数: 0

Enhanced linearity of AlGaN/GaN HEMTs via dual-gate configuration for RF amplifier applications 通过射频放大器应用的双栅极配置增强了AlGaN/GaN hemt的线性度

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-04-14 DOI: 10.1016/j.sse.2025.109127

Haowen Guo , Wenbo Ye , Junmin Zhou , Yitian Gu , Han Gao , Xinbo Zou

{"title":"Enhanced linearity of AlGaN/GaN HEMTs via dual-gate configuration for RF amplifier applications","authors":"Haowen Guo , Wenbo Ye , Junmin Zhou , Yitian Gu , Han Gao , Xinbo Zou","doi":"10.1016/j.sse.2025.109127","DOIUrl":"10.1016/j.sse.2025.109127","url":null,"abstract":"<div><div>This study investigates RF linearity performance of a GaN dual-gate HEMT, focusing on its two-tone intermodulation characteristics. The dual-gate configuration is implemented to enhance linearity performance by reducing feedback capacitance to 41.8 fF/mm, achieving a reduction of 73 % when compared to conventional single-gate HEMTs. The dual-gate device showcases a small-signal gain of 23.5 dB at 2.1 GHz, which remains constant regardless of DC gate bias voltage <em>V<sub>B</sub></em>. Intermodulation distortion could be mitigated by increasing <em>V<sub>B</sub></em>, as evidenced by device’s highest OIP3 of 30.1 dBm at <em>V<sub>B</sub></em> of 3 V and a drain voltage of 20 V. Additionally, the OIP3/<em>P<sub>DC</sub></em> reaches a peak value of 10.6 dB at <em>V<sub>DS</sub></em> of 5 V. A comparison between the dual-gate HEMT and a conventional single-gate device demonstrates a 3.7 dB gain increase of and a linearity improvement of 5.9 dB. These results highlight the advantageous power gain and high linearity of the dual-gate structure, indicating its considerable potential for RF amplifier applications that require minimum signal distortion.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109127"},"PeriodicalIF":1.4,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143839177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0