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Assessing the impact of process and design variations on reliability of complementary FET 评估工艺和设计变化对互补场效应管可靠性的影响
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-30 DOI: 10.1016/j.sse.2025.109226
Ankit Dixit , Sandeep Kumar , Naveen Kumar , Deven H. Patil , S. Dasgupta , Navjeet Bagga , Luiz Felipe Aguinsky , Vihar Georgiev
{"title":"Assessing the impact of process and design variations on reliability of complementary FET","authors":"Ankit Dixit ,&nbsp;Sandeep Kumar ,&nbsp;Naveen Kumar ,&nbsp;Deven H. Patil ,&nbsp;S. Dasgupta ,&nbsp;Navjeet Bagga ,&nbsp;Luiz Felipe Aguinsky ,&nbsp;Vihar Georgiev","doi":"10.1016/j.sse.2025.109226","DOIUrl":"10.1016/j.sse.2025.109226","url":null,"abstract":"<div><div>This paper comprehensively analyzes the reliability concerns of the Complementary FET (CFET), engrossing the design parameters and the variability effects. The impact of process-induced variabilities, such as random dopant distribution (RDD), line edge roughness (LER), and metal gate granularity (MGG), is extensively studied through well-calibrated TCAD models. Variation aware compact model based statistical analysis is used to analyze 100 random device samples, which shows a significant spread in the I<sub>DS</sub>-V<sub>GS</sub> curve (transfer characteristics). Electrical performance based on the grain size and fin width is also analyzed on both n and p-type device. Therefore, the variation in threshold voltage (V<sub>th</sub>) is used to predict the early aging of the devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109226"},"PeriodicalIF":1.4,"publicationDate":"2025-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of lateral source/drain growth profile for improving RC delay in nanosheet field-effect transistor 改善纳米片场效应晶体管RC延迟的横向源极/漏极生长曲线优化
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-30 DOI: 10.1016/j.sse.2025.109227
Jin Ho Park , Jae Woog Jung , Hyunwoo Kim
{"title":"Optimization of lateral source/drain growth profile for improving RC delay in nanosheet field-effect transistor","authors":"Jin Ho Park ,&nbsp;Jae Woog Jung ,&nbsp;Hyunwoo Kim","doi":"10.1016/j.sse.2025.109227","DOIUrl":"10.1016/j.sse.2025.109227","url":null,"abstract":"<div><div>In the advancing sub-3 nm technology node, device evolution has progressed from FinFET to gate-all-around based nanosheet architectures (NSFETs). This transition addresses the limitations of FinFETs, where scaling down leads to a reduced number of fins, maintaining a quantized width and resulting in decreased current drivability. In contrast, NSFETs offer flexible width design similar to traditional planar structures and allow for multi-channel stacking, increasing current and making them an attractive candidate from a circuit design perspective. However, NSFETs also faces challenges in device performance due to increased parasitic RC components, despite improved gate controllability.</div><div>In this work, we analyzed parasitic RC components in NSFETs with different source/drain growth profiles using 3D TCAD simulations and then examined the RC delay to determine the source/drain growth profile that exhibits optimal device performance. Furthermore, we investigated self-heating effects (SHEs) to evaluate heat dissipation across different source/drain profiles, integrating these findings with RC delay analyses to propose the optimal growth profile.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109227"},"PeriodicalIF":1.4,"publicationDate":"2025-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of back-biasing on the series resistance in ultrathin SOI devices 背偏对超薄SOI器件串联电阻的影响
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-30 DOI: 10.1016/j.sse.2025.109225
Yu Yan , Cunhua Dou , Xuan Zhang , Weijia Song , Zhiyu Tang , Binhong Li , Jing Wan , Huabin Sun , Xing Zhao , Yun Wang , Yong Xu , Sorin Cristoloveanu
{"title":"Impact of back-biasing on the series resistance in ultrathin SOI devices","authors":"Yu Yan ,&nbsp;Cunhua Dou ,&nbsp;Xuan Zhang ,&nbsp;Weijia Song ,&nbsp;Zhiyu Tang ,&nbsp;Binhong Li ,&nbsp;Jing Wan ,&nbsp;Huabin Sun ,&nbsp;Xing Zhao ,&nbsp;Yun Wang ,&nbsp;Yong Xu ,&nbsp;Sorin Cristoloveanu","doi":"10.1016/j.sse.2025.109225","DOIUrl":"10.1016/j.sse.2025.109225","url":null,"abstract":"<div><div>The universal burden of series resistance in short-channel MOSFETs is even more critical in ultrathin transistors where the sheet resistance of source and drain terminals is high. However, FD-SOI devices benefit from the back-gate action which can also modulate the series resistance. Several methods for series resistance extraction are examined. Unlike an advanced FD-SOI MOSFET with highly-doped raised terminals, the junctionless transistors (with either conventional or core–shell architecture) exhibit higher series resistance, strongly dependent on back-gate voltage.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109225"},"PeriodicalIF":1.4,"publicationDate":"2025-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhancing carrier transport in AlGaN/GaN HEMTs through structural optimization and transconductance modeling 通过结构优化和跨电导建模增强AlGaN/GaN hemt中的载流子输运
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-29 DOI: 10.1016/j.sse.2025.109222
Hyo-Joung Kim , Walid Amir , Surajit Chakraborty , Ju-Won Shin , Ki-Young Shin , Hyuk-Min Kwon , Tae-Woo Kim
{"title":"Enhancing carrier transport in AlGaN/GaN HEMTs through structural optimization and transconductance modeling","authors":"Hyo-Joung Kim ,&nbsp;Walid Amir ,&nbsp;Surajit Chakraborty ,&nbsp;Ju-Won Shin ,&nbsp;Ki-Young Shin ,&nbsp;Hyuk-Min Kwon ,&nbsp;Tae-Woo Kim","doi":"10.1016/j.sse.2025.109222","DOIUrl":"10.1016/j.sse.2025.109222","url":null,"abstract":"<div><div>In GaN-based High-Electron Mobility Transistors (HEMTs), the carrier transport properties of the 2-Dimensional Electron Gas (2DEG), specifically the saturation velocity (<em>υ<sub>sat</sub></em>) and effective mobility (<em>μ<sub>n_eff</sub></em>,), are critical determinants of device performance. To enhance these properties, we conducted structural optimizations, which included reducing the Al mole fraction in the Al<sub>x</sub>Ga<sub>1-x</sub>N barrier and introducing an AlGaN back barrier. Recognizing the limitations of traditional extraction techniques, we employed transconductance modeling to accurately extract effective mobility and saturation velocity values. The implementation of the AlGaN back barrier resulted in an effective mobility enhancement to 748 cm<sup>2</sup>/V·s. Additionally, reducing the Al mole fraction in the Al<sub>x</sub>Ga<sub>1-x</sub>N top barrier led to an effective mobility improvement of 484 cm<sup>2</sup>/V·s. These findings provide valuable insights into the design of epitaxial structures for AlGaN/GaN HEMTs aimed at achieving superior performance in future applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109222"},"PeriodicalIF":1.4,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the role of power dissipation in the Post-BD behavior of FDSOI NanoWire FETs 功率损耗对FDSOI纳米线场效应管后bd行为的影响
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-29 DOI: 10.1016/j.sse.2025.109228
R. Goyal, A. Crespo-Yepes, M. Porti, R. Rodriguez, M. Nafria
{"title":"On the role of power dissipation in the Post-BD behavior of FDSOI NanoWire FETs","authors":"R. Goyal,&nbsp;A. Crespo-Yepes,&nbsp;M. Porti,&nbsp;R. Rodriguez,&nbsp;M. Nafria","doi":"10.1016/j.sse.2025.109228","DOIUrl":"10.1016/j.sse.2025.109228","url":null,"abstract":"<div><div>Dielectric Breakdown, which has been associated with the progressive wear-out of the gate dielectric, has been one of the most detrimental failure mechanisms in CMOS devices. With downscaling, new device architectures and/or materials have been introduced, so, it is necessary to evaluate the BD impact at device (and circuit) level in these new structures. In this work, the dielectric BD and the post-BD behavior in largely scaled FDSOI nanowire transistors with high-k gate dielectric have been characterized, using the energy and the power dissipated by the device under test as key parameters. The experimental results evidence the presence of new detrimental effects for the device’s integrity beyond the traditional dielectric BD.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109228"},"PeriodicalIF":1.4,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144933522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Non-uniform matching performances in mesa-isolated SOI MOSFETs 台面隔离SOI mosfet的非均匀匹配性能
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-26 DOI: 10.1016/j.sse.2025.109224
Pierre Lhéritier , Daphnée Bosch , Giovanni Romano , Fabienne Ponthenier , Sylvain Joblot , Joris Lacord
{"title":"Non-uniform matching performances in mesa-isolated SOI MOSFETs","authors":"Pierre Lhéritier ,&nbsp;Daphnée Bosch ,&nbsp;Giovanni Romano ,&nbsp;Fabienne Ponthenier ,&nbsp;Sylvain Joblot ,&nbsp;Joris Lacord","doi":"10.1016/j.sse.2025.109224","DOIUrl":"10.1016/j.sse.2025.109224","url":null,"abstract":"<div><div>This work studies the threshold voltage mismatch of mesa-isolated SOI pMOSFETs through a breakdown between edge and center contributions. Pelgrom’s law is followed if a proper care is taken in the Vt extraction method. Applied to pMOS devices we observed that despite its parasitic nature, the edge transistor mismatch is as good as that of the center, regardless of channel doping and back-gate bias. Mismatch degradation in reverse back-bias mode is observed and attributed to the presence of floating body effects.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109224"},"PeriodicalIF":1.4,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon-oxide resistive switching memory based on the HSQ layer 基于HSQ层的氧化硅电阻开关存储器
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-26 DOI: 10.1016/j.sse.2025.109223
Piotr Wiśniewski , Andrzej Mazurak , Alicja Kądziela , Maciej Filipiak , Bartłomiej Stonio , Romuald B. Beck
{"title":"Silicon-oxide resistive switching memory based on the HSQ layer","authors":"Piotr Wiśniewski ,&nbsp;Andrzej Mazurak ,&nbsp;Alicja Kądziela ,&nbsp;Maciej Filipiak ,&nbsp;Bartłomiej Stonio ,&nbsp;Romuald B. Beck","doi":"10.1016/j.sse.2025.109223","DOIUrl":"10.1016/j.sse.2025.109223","url":null,"abstract":"<div><div>In this work, we study the silicon-oxide resistive switching memory based on the hydrogen silsesquioxane (HSQ) layer. We fabricated the Al/HSQ/n++ − Si RRAM (Resistive Random Access Memory) devices and performed electrical characterization. Transport mechanisms for different voltage ranges in High Resistance State (HRS) and Low Resistance State (LRS) were identified and analyzed. We show that spin on the silicon oxide layer can result in good resistive switching properties that can be utilized in the design and fabrication of RRAM devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109223"},"PeriodicalIF":1.4,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144933521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Statistical enhancement in two-particle Device Monte Carlo 蒙特卡罗双粒子器件的统计增强
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-26 DOI: 10.1016/j.sse.2025.109210
Josef Gull, Hans Kosina
{"title":"Statistical enhancement in two-particle Device Monte Carlo","authors":"Josef Gull,&nbsp;Hans Kosina","doi":"10.1016/j.sse.2025.109210","DOIUrl":"10.1016/j.sse.2025.109210","url":null,"abstract":"<div><div>A novel two-particle Monte Carlo (MC) transport model has been developed and applied to determine the energy distribution function (EDF) in a MOSFET. A dedicated statistical enhancement algorithm enhances the number of samples at higher energies. A comparison with the well-established one-particle MC method and a related enhancement method is presented.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109210"},"PeriodicalIF":1.4,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144902954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design guidelines for Gr-MoS2 based DS-FETs 基于Gr-MoS2的ds - fet设计指南
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-23 DOI: 10.1016/j.sse.2025.109216
Tommaso Ugolini, Elena Gnani
{"title":"Design guidelines for Gr-MoS2 based DS-FETs","authors":"Tommaso Ugolini,&nbsp;Elena Gnani","doi":"10.1016/j.sse.2025.109216","DOIUrl":"10.1016/j.sse.2025.109216","url":null,"abstract":"<div><div>As the development of Dirac-Source Field-Effect Transistors (DS-FETs) progresses, there is an increasing need for a robust, flexible, and agile simulation framework capable of evaluating device performance across a range of operating conditions. This work addresses that need by coupling a two-dimensional (2D) Poisson solver with a quantum transport model under the ballistic transport regime. This simulation approach is employed to analyze the electrical characteristics of a DS-FET realized with the heterojunction of graphene and monolayer MoS<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>. In addition, the impact of gate-to-channel alignment on device performance is systematically investigated. Simulation results underscore the critical role of full gate overlap with the semiconducting region and substantiate the feasibility of DS-FETs based on these two materials.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109216"},"PeriodicalIF":1.4,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144895146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Boosting the electrical performance of solar cells by using PIN diode structure with different layout styles controlled by MOS capacitor 利用MOS电容控制不同布局风格的PIN二极管结构提高太阳能电池的电性能
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-23 DOI: 10.1016/j.sse.2025.109217
Fernando Pizzo Ribeiro, Egon H.S. Galembeck, Salvador Pinillos Gimenez
{"title":"Boosting the electrical performance of solar cells by using PIN diode structure with different layout styles controlled by MOS capacitor","authors":"Fernando Pizzo Ribeiro,&nbsp;Egon H.S. Galembeck,&nbsp;Salvador Pinillos Gimenez","doi":"10.1016/j.sse.2025.109217","DOIUrl":"10.1016/j.sse.2025.109217","url":null,"abstract":"<div><div>In this study, an innovative solar cell (SC) design is proposed and analyzed using the Sentaurus Technology Computer-Aided Design (TCAD) simulator. Departing from conventional rectangular architecture, a half-circular geometry is introduced to improve light absorption and enhance electrical performance. The simulation framework models the solar cell’s behavior under standard test conditions, incorporating realistic material properties and stratified layer structures. Key electrical performance metrics, Fill Factor (FF), and conversion Efficiency are evaluated. The results demonstrate that the half-circular configuration achieves an energy conversion efficiency of 15.33 %, and an FF of 74.2 %. This work lays the groundwork for future experimental validation and encourages the investigation of alternative geometries to improve photovoltaic device performance further.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109217"},"PeriodicalIF":1.4,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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