Yelim Jeon , Hyungju Noh , Seungwon Go , Sangwan Kim
{"title":"Rigorous analysis on the operating mechanism of gate-injection ferroelectric flash","authors":"Yelim Jeon , Hyungju Noh , Seungwon Go , Sangwan Kim","doi":"10.1016/j.sse.2025.109153","DOIUrl":null,"url":null,"abstract":"<div><div>In this paper, the operation mechanism of gate-injection ferroelectric flash (GI-FeFlash) is studied through technology computer-aided design (TCAD) simulations. It reveals that GI-FeFlash exhibits an extraordinarily large memory window (MW) compared to the sum of MWs of a ferroelectric field-effect transistor (FeFET) and a charge trap flash (CTF), attributed to the synergistic effects between the two mechanisms: a polarization switching and a charge trapping. These synergistic effects can be analyzed by two phenomena: 1) a trap-assisted polarization switching (TAPS) and 2) a polarization-assisted charge trapping (PACT). In the case of TAPS, the trapped charges in the charge trap layer (CTL) enhance the polarization in the ferroelectric (FE) layer by increasing the electric field of the blocking oxide (i.e., FE layer). On the other hand, in the case of PACT, the polarization in the FE layer helps the charge injection into the CTL by increasing the electric field of the tunnel oxide (TO). Furthermore, TAPS and PACT are also verified by the analytical models based on Gauss’s law. Therefore, GI-FeFlash can achieve a large MW (∼14.9 V) with a low-program/erase voltage and a fast-speed operation through the complementary relations between the two mechanisms.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109153"},"PeriodicalIF":1.4000,"publicationDate":"2025-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S003811012500098X","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, the operation mechanism of gate-injection ferroelectric flash (GI-FeFlash) is studied through technology computer-aided design (TCAD) simulations. It reveals that GI-FeFlash exhibits an extraordinarily large memory window (MW) compared to the sum of MWs of a ferroelectric field-effect transistor (FeFET) and a charge trap flash (CTF), attributed to the synergistic effects between the two mechanisms: a polarization switching and a charge trapping. These synergistic effects can be analyzed by two phenomena: 1) a trap-assisted polarization switching (TAPS) and 2) a polarization-assisted charge trapping (PACT). In the case of TAPS, the trapped charges in the charge trap layer (CTL) enhance the polarization in the ferroelectric (FE) layer by increasing the electric field of the blocking oxide (i.e., FE layer). On the other hand, in the case of PACT, the polarization in the FE layer helps the charge injection into the CTL by increasing the electric field of the tunnel oxide (TO). Furthermore, TAPS and PACT are also verified by the analytical models based on Gauss’s law. Therefore, GI-FeFlash can achieve a large MW (∼14.9 V) with a low-program/erase voltage and a fast-speed operation through the complementary relations between the two mechanisms.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.