Solid-state Electronics最新文献_第4页

Analysis of leakage current mechanisms in AlInGaN/GaN metal-insulator-semiconductor capacitors AlInGaN/GaN金属绝缘体-半导体电容器漏电流机理分析

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-11 DOI: 10.1016/j.sse.2025.109292

Guiyu Shen , Ying Wang , Yulong Fang , Yongchuan Tang , He Guan

{"title":"Analysis of leakage current mechanisms in AlInGaN/GaN metal-insulator-semiconductor capacitors","authors":"Guiyu Shen , Ying Wang , Yulong Fang , Yongchuan Tang , He Guan","doi":"10.1016/j.sse.2025.109292","DOIUrl":"10.1016/j.sse.2025.109292","url":null,"abstract":"<div><div>For emerging 5G millimeter-wave base stations and automotive radar systems operating in the V/W bands, suppressing gate leakage currents in AlInGaN/GaN MIS capacitors is critical to mitigate energy losses exceeding 15 % and thermal runaway risks under high-power RF conditions. This study systematically investigates the leakage mechanisms in AlInGaN/GaN Metal-Insulator-Semiconductor (MIS) capacitors, focusing on the influence of electrode geometry. We analyze the factors governing leakage behavior by fabricating devices with a series of electrode dimensions and spacings, and conducting comprehensive current–voltage (I-V) and capacitance–voltage (C-V) measurements. The results demonstrate that reducing electrode spacing intensifies local electric field concentration, enhancing trap-assisted tunneling at the interface and thereby increasing leakage current density. Conversely, increasing electrode size and spacing improves the uniformity of the electric field distribution and significantly mitigates the leakage currents. In addition, C-V measurement shows that the Si<sub>3</sub>N<sub>4</sub> passivation process can effectively suppress the defects of the heterojunction interface. After passivation, the interface state density decreases to 6.1 × 10<sup>11</sup> cm<sup>−2</sup> eV<sup>−1</sup>. Further analysis elucidates the voltage-dependent nature of leakage mechanisms: ohmic conduction dominates in low-field regions, while Schottky emission and Frenkel-Poole emission contribute in medium-to-high fields, with Fowler-Nordheim tunneling prevails under high electric fields. These findings emphasize the critical role of optimizing electrode geometries and interface passivation strategies in enhancing device reliability. This work provides theoretical insights and experimental guidance for advancing high-frequency, high-power GaN-based devices for emerging applications in communications and RF technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109292"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling of RRAM based PUF: a case study 基于RRAM的PUF建模：一个案例研究

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-21 DOI: 10.1016/j.sse.2025.109267

Kamil Ber , Piotr Wiśniewski

引用次数: 0

Markov model describing progressive degradation of local percolation path in thin oxides 描述薄氧化物局部渗透路径逐步退化的马尔可夫模型

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-28 DOI: 10.1016/j.sse.2025.109266

Sara Sacchi , Anirudh Varanasi , Robin Degraeve , Andrea Vici , Giorgio Molinaro , Jacopo Franco , Philippe Roussel , Ben Kaczer , Clement Merckling

{"title":"Markov model describing progressive degradation of local percolation path in thin oxides","authors":"Sara Sacchi , Anirudh Varanasi , Robin Degraeve , Andrea Vici , Giorgio Molinaro , Jacopo Franco , Philippe Roussel , Ben Kaczer , Clement Merckling","doi":"10.1016/j.sse.2025.109266","DOIUrl":"10.1016/j.sse.2025.109266","url":null,"abstract":"<div><div>Time-Dependent Dielectric Breakdown (TDDB) remains a critical reliability challenge in advanced CMOS technologies using thin <span><math><msub><mrow><mi>SiO</mi></mrow><mrow><mn>2</mn></mrow></msub></math></span>/High-k oxides. While extensive research focused on the formation of conductive filaments and the physics and statistics of soft breakdown and hard breakdown events, the intermediate wear-out phase — where a localized leakage path gradually increases in conductivity — has not been thoroughly analyzed or modeled. Firstly, this work addresses this gap by experimentally isolating and analyzing the wear-out phase with a Machine learning-assisted analysis, revealing key statistical features of wear-out and its dependence on stress voltage. Secondly, a Monte Carlo-implemented Markov model is used to simulate the localized degradation of a one-defect percolation path by means of a thermally activated defect creation and deactivation/annealing process, governed by an Arrhenius-like transition probability function. Simulations qualitatively reproduce the observed experimental degradation trends, with discrepancies in voltage dependence and initial defect accumulation, highlighting the need for a more nuanced approach, including statistical distributions of atomic bond strengths.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109266"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Scattering matrix-based low computational cost model for the device and circuit co-simulation of phosphorene tunnel field-effect transistors 基于散射矩阵的磷二烯隧道场效应晶体管器件与电路联合仿真的低计算成本模型

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-01 DOI: 10.1016/j.sse.2025.109270

Kosuke Yamaguchi, Satofumi Souma

引用次数: 0

Design of high robustness DDSCR with embedded gate-controlled diodes and Schottky diodes 嵌入式门控二极管和肖特基二极管的高鲁棒性DDSCR设计

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-02 DOI: 10.1016/j.sse.2025.109283

Yitao Wang , Shuoxin Ji , Yang Wang

{"title":"Design of high robustness DDSCR with embedded gate-controlled diodes and Schottky diodes","authors":"Yitao Wang , Shuoxin Ji , Yang Wang","doi":"10.1016/j.sse.2025.109283","DOIUrl":"10.1016/j.sse.2025.109283","url":null,"abstract":"<div><div>Due to the harsh working environments of Input/Output (I/O) pins, the electro-static discharge (ESD) protection devices of these ports often require high robustness. To design highly robust ESD protection devices with dual polarities, the Gate-controlled dual direction silicon controlled rectifier (GCDDSCR) and a DDSCR embedded with Schottky barrier diode (SBD-GCDDSCR) structures are designed and studied in this article as standalone devices for primary protection. The gate-controlled diodes and Schottky diodes are integrated into the simple DDSCR structure to enhance its robustness while reducing the on-resistance. The inclusion of gate diodes introduced an additional current path near the surface, improving space utilization in the longitudinal direction of the device, and the addition of Schottky junctions placed adjacent to the Anode and Cathode can provide additional electron extraction paths. Both methods contribute in a more uniform current distribution, improving the robustness of the device. Two-dimensional device simulation based on a classical set of equations was employed to investigate its electrical behavior during an ESD event. Based on the 0.18 μm CMOS process, all structures were fabricated into 6-finger devices with a finger length of 50 μm. The Transmission Line Pulse (TLP) testing method was used to evaluate their ESD characteristics, revealing that the addition of the gate-controlled diodes and Schottky shunt paths improved robustness. The proposed SBD-GCDDSCR structure demonstrated superior robustness under ESD stress, with a failure current exceeding 19 A in both forward and reverse directions, and its V<sub>t2</sub> in strong saturation regime is around 48 V.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109283"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploring temperature effects in dielectric and impedance spectroscopy of TiOx-Incorporated HfOx thin film 探讨含tiox - HfOx薄膜介电和阻抗谱的温度效应

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-27 DOI: 10.1016/j.sse.2025.109282

Rezwana Sultana, Karimul Islam, Robert Mroczyński

{"title":"Exploring temperature effects in dielectric and impedance spectroscopy of TiOx-Incorporated HfOx thin film","authors":"Rezwana Sultana, Karimul Islam, Robert Mroczyński","doi":"10.1016/j.sse.2025.109282","DOIUrl":"10.1016/j.sse.2025.109282","url":null,"abstract":"<div><div>In this work, the temperature effect in dielectric, impedance, and leakage current characteristics of TiO<sub>x</sub>-incorporated HfO<sub>x</sub> (HTO) thin film integrated into metal–oxide–semiconductor (MOS) structure were investigated. The thin HTO layer was prepared using a pulsed-DC reactive magnetron sputtering technique. The successful preparation of HTO has been confirmed by analyzing the spectral profile of the refractive index. Energy dispersive X-ray analysis was employed to determine the elemental composition of the oxide film. The capacitance-frequency study of the Al/HTO/<em>p</em>-Si structure was carried out over a temperature range of 25 to 100 °C and a frequency range of 1 kHz to 3.5 MHz. The experimental results indicate that the dielectric constant, dielectric loss, and AC conductivity increase with rising temperature. Detailed impedance spectroscopy analysis reveals that the composite film follows a non-Debye type relaxation process signifying thermally activated dielectric relaxation and a reduced relaxation time with increasing temperature. The current–voltage characteristics demonstrated that the leakage current of the device increases with temperature, while exhibiting a nominal value within the measured temperature range. The findings underscore the influence of temperature on the dielectric, impedance, and leakage current properties of HTO films, providing key insights into enhancing the reliability of Al/HTO/<em>p</em>-Si MOS devices, particularly under high-temperature operation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109282"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

In-depth DC characterization of asymmetric vertical nanowire Accumulation-Mode junctionless GAA pMOSFETs on SOI from 300 K to 400 K 非对称垂直纳米线累积模式无结GAA pmosfet在300 K至400 K SOI上的深入直流特性

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-07 DOI: 10.1016/j.sse.2025.109290

A. Tahiat , B. Cretu , A. Veloso , E. Simoen

{"title":"In-depth DC characterization of asymmetric vertical nanowire Accumulation-Mode junctionless GAA pMOSFETs on SOI from 300 K to 400 K","authors":"A. Tahiat , B. Cretu , A. Veloso , E. Simoen","doi":"10.1016/j.sse.2025.109290","DOIUrl":"10.1016/j.sse.2025.109290","url":null,"abstract":"<div><div>In this article, we present an in-depth investigation of the direct current (DC) characteristics of asymmetric vertical nanowire (VNW) accumulation-mode junctionless (JL) gate-all-around (GAA) pMOSFETs fabricated on silicon-on-insulator (SOI) substrates. Measurements were performed over a temperature range from 300 K to 400 K in both linear and saturation regimes. Our results reveal significant temperature and polarization-dependent behaviors. It has been demonstrated that the nanowire diameter impacts the DC performance. A nanowire diameter larger than 20 nm leads to a significant increase in off-state leakage current and a higher on-state drive current compared to smaller diameters. Although a larger diameter improves the on-state current, it degrades the subthreshold swing (SS), indicating weaker electrostatic control. Furthermore, using the top electrode as either the drain (forward operation mode) or the source (reverse operation mode) significantly affects device performance due to their asymmetric architecture. In the forward mode, a higher off-state leakage current is observed, while in the reverse mode, the on-state saturation current is higher. This asymmetry may be attributed to asymmetric access resistances (<span><math><mrow><msub><mi>R</mi><mi>S</mi></msub><mspace></mspace><mo>></mo><mspace></mspace><msub><mi>R</mi><mi>D</mi></msub></mrow></math></span>). From high-temperature measurements, using different series-resistance-free parameter-extraction (Y-function-based) methodologies, it is observed that the series resistance of the devices remains unchanged, and the low-field mobility is mainly limited by Coulomb scattering. This study provides a better understanding of the behavior and performance of VNW accumulation-mode JL GAA pMOSFETs and paves the way for further optimization.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109290"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of PN passivation on MOSFETs performance in 28 nm FD-SOI PN钝化对28 nm FD-SOI中mosfet性能的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-11-15 DOI: 10.1016/j.sse.2025.109293

M. Vanbrabant , M. Rack , A. Cathelin , J.-P. Raskin , V. Kilchytska

引用次数: 0

Exploring low-frequency noise dynamics in a-IGZO TFTs: Unveiling the impact of contact metal variations for advanced semiconductor applications 探索a-IGZO TFTs中的低频噪声动力学：揭示接触金属变化对先进半导体应用的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-26 DOI: 10.1016/j.sse.2025.109271

Junseong Park , Haesung Kim , Sung-Jin Choi , Dae Hwan Kim , Dong Myong Kim , Jong-Ho Bae

{"title":"Exploring low-frequency noise dynamics in a-IGZO TFTs: Unveiling the impact of contact metal variations for advanced semiconductor applications","authors":"Junseong Park , Haesung Kim , Sung-Jin Choi , Dae Hwan Kim , Dong Myong Kim , Jong-Ho Bae","doi":"10.1016/j.sse.2025.109271","DOIUrl":"10.1016/j.sse.2025.109271","url":null,"abstract":"<div><div>Amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors (TFTs) are highly promising for applications such as embedded memory in CMOS BEOL 2T-DRAM due to their low leakage current and high field-effective mobility. This study systematically analyzes the a-IGZO TFTs, focusing on their low-frequency noise (LFN) characteristics with varying contact metals. We fabricated the staggered a-IGZO TFTs utilizing gate, source and drain metals with different work functions (Mo ∼ 4.6 eV and Pd ∼ 5.1 eV) to investigate the impact of electrode materials on device performance. The findings demonstrate distinct LFN characteristics influenced by the contact properties. Specifically, the device with Mo source and drain exhibits behavior consistent with carrier mobility fluctuation (CMF), while the device with Pd shows Schottky barrier height fluctuation in low current regions and carrier number fluctuation (CNF) in high current regions. This differentiation in noise characteristics is crucial for understanding and optimizing the device operation mechanism, performance and reliability in advanced memory applications. The result highlights the importance of selecting appropriate contact materials to minimize noise and enhance device performance, providing valuable insights for the design and development of high-performance a-IGZO TFT-based memory technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109271"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance evaluation of SiC MOSFET-based converter for EV fast charging systems 基于SiC mosfet的电动汽车快速充电变换器性能评价

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2026-01-01 Epub Date: 2025-10-27 DOI: 10.1016/j.sse.2025.109286

Quoc Tuan Tran , Nguyen Phuong Tran

引用次数: 0