Solid-state Electronics最新文献

{"title":"Determination of source series resistances for InP HEMT under normal bias condition","authors":"Ao Zhang ,&nbsp;Jianjun Gao","doi":"10.1016/j.sse.2024.108975","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108975","url":null,"abstract":"<div><p>A novel approach to determine the source series resistance for InP HEMT device, which combines the DC characteristics measurement and S-parameters measurement under normal bias condition is developed in this paper. Three HEMT devices with different gatewidth have been used to verify the validity of the method, and good agreement is obtained between modeled and measured S-parameters and noise parameters.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"219 ","pages":"Article 108975"},"PeriodicalIF":1.4,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141478672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of ISFET for KCl sensing","authors":"Pedro H. Duarte ,&nbsp;Ricardo C. Rangel ,&nbsp;Katia R.A. Sasaki ,&nbsp;Joao A. Martino","doi":"10.1016/j.sse.2024.108974","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108974","url":null,"abstract":"<div><p>This work presents the fabrication and electrical characterization of the Ion Sensitive Field Effect Transistor (ISFET) exposed to potassium chloride (KCl) solutions. The focus of the study is to compare two measurements methods and verify the effects of these methods in the device threshold voltage (V_TH) sensitivity to the different KCl concentrations. First, a reference electrode (a platinum needle) is placed in the sample solution over the gate area of the device, demonstrating that the threshold voltage decreases with the increase of the KCl concentration. The method shows a sensitivity of 10.44 mV/mM for the low KCl concentration range (0 to 10 mM) and 0.5 mV/mM for the higher KCl concentration range (10 to 100 mM). The second method involves inserting a second platinum electrode into the solution on the field oxide. This method proposes the KCl electrolysis to increase the selectivity for potassium ions. The result allows the next steps for potassium sensing biosensor application with selective membranes.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"219 ","pages":"Article 108974"},"PeriodicalIF":1.4,"publicationDate":"2024-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141481896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Editorial “Selected papers from the international conference on simulation of semiconductor processes and devices 2022”","authors":"Francisco Gamiz,&nbsp;Carlos Sampedro,&nbsp;Luca Donetti,&nbsp;Carlos Navarro","doi":"10.1016/j.sse.2024.108973","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108973","url":null,"abstract":"","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"219 ","pages":"Article 108973"},"PeriodicalIF":1.4,"publicationDate":"2024-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141582581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Switching layer optimization in Co-based CBRAM for >105 memory window in sub-100 µA regime","authors":"Yongjun Cho ,&nbsp;Bo Soo Kang ,&nbsp;Pankaj Kumbhare ,&nbsp;Romain Delhougne ,&nbsp;Laura Nyns ,&nbsp;Ming Mao ,&nbsp;Ludovic Goux ,&nbsp;Gouri Sankar Kar ,&nbsp;Attilio Belmonte","doi":"10.1016/j.sse.2024.108964","DOIUrl":"10.1016/j.sse.2024.108964","url":null,"abstract":"<div><p>Co/HfO₂-based CBRAM stacks are optimized to enlarge the memory window for low-current (50 µA) operation. First, we dope the switching layer with Si to decrease the pristine current, thus enlarging the memory window. Then, we reduce the forming voltage by scaling the Si-doped HfO₂ thickness. Finally, we extend the endurance lifetime and reduce the write time by introducing a hygroscopic oxide, LaSiO, in combination with HfSiO, to enhance Co ion hopping through hydroxyl groups. We further outline the important role of the position of the hygroscopic layer with respect to the Co active electrode in enlarging the memory window of the CBRAM device up to &gt; 10⁵.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"219 ","pages":"Article 108964"},"PeriodicalIF":1.7,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141399629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on MOS shunt LVTSCR for ESD application","authors":"Dongyan Zhao ,&nbsp;Yipeng Chen ,&nbsp;Shicong Zhou ,&nbsp;Xinyu Zhu ,&nbsp;Yidong Yuan ,&nbsp;Yi Hu ,&nbsp;Tianting Zhao ,&nbsp;Xiaojuan Li ,&nbsp;Shurong Dong","doi":"10.1016/j.sse.2024.108963","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108963","url":null,"abstract":"<div><p>Continuously scaling down ICs result in more stringent electrostatic discharge (ESD) protection design requirements. Compared with other devices, silicon-controlled rectifier (SCR) has become the first choice for its area efficiency and robustness. In order to improve the latch-up issue of SCR, various schemes have been proposed. A simple method is to extend the SCR path length, which will result in the enlarged ON resistance. Segment technology is also used to improve the holding voltage of SCR, but it will shrink the effective emitter area and lead to the serious degradation of ESD robustness. MS-LVTSCR is used to protect CMOS input ports. The circuit operating voltage is 3.3V and the gate oxide DC breakdown voltage is 19V so that considering the safety margin, the ESD window is from 3.63V to 17.1V. This work proposes a novel MOS shunt low-voltage trigger silicon-controlled rectifier (MS-LVTSCR) electrostatic discharge protection device by inserting an embedded PMOS structure. Compared with the conventional LVTSCR, the proposed MS-LVTSCR achieves 53% improvement in the holding voltage and still maintains high ESD robustness with a current level of 31.5 mA/<span><math><mi>μ</mi></math></span>m without more device area consumption. In addition, both the TCAD simulation and theoretical analysis were carried out to explore the principle of current shunt effect to improve holding voltage. The extra shunt paths will weaken the conductance modulation effect of the main drift region in the main SCR path and its holding voltage can be further raised by reducing the proportion of main drift region current in the total current. We also conducted detailed studies on the mechanisms and geometry effects of this newly proposed structure via experimental validations.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"218 ","pages":"Article 108963"},"PeriodicalIF":1.7,"publicationDate":"2024-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141243499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electron and spin transport in semiconductor and magnetoresistive devices","authors":"Viktor Sverdlov ,&nbsp;Siegfried Selberherr","doi":"10.1016/j.sse.2024.108962","DOIUrl":"10.1016/j.sse.2024.108962","url":null,"abstract":"<div><p>As the scaling of CMOS-based technology shows signs of an imminent saturation, employing the second intrinsic electron characteristics – the electron spin – is attractive to further boost the performance of integrated circuits and to introduce new computational paradigms. The spin promises to offer an additional functionality to charge-based CMOS circuitry. Spin injection and spin manipulation by gate-induced electrics field at room temperatures were successfully demonstrated in semiconductor channels, expectations that such spin-driven devices appear in digital circuits to complement or even replace CMOS become credible.</p><p>On the memory side, the nonvolatile CMOS-compatible spin-transfer torque (STT) and the spin–orbit torque magnetoresistive random access memories (MRAMs) are already competing with flash memory and even SRAM for embedded applications.</p><p>To accurately model spin and charge transport and torques in magnetic tunnel junctions, we innovatively extend the spin and charge transport equations to multi-layered structures consisting of normal and ferromagnetic metal layers separated by tunnel barriers. We validate our approach by modeling the magnetization dynamics in ultra-scaled MRAM cells. A multi-bit operation is predicted in an MRAM cell with a composite free layer.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"218 ","pages":"Article 108962"},"PeriodicalIF":1.7,"publicationDate":"2024-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141132307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature- and variability-aware compact modeling of ferroelectric FDSOI FET for memory and emerging applications","authors":"Swetaki Chatterjee ,&nbsp;Shubham Kumar ,&nbsp;Amol Gaidhane ,&nbsp;Chetan Kumar Dabhi ,&nbsp;Yogesh Singh Chauhan ,&nbsp;Hussam Amrouch","doi":"10.1016/j.sse.2024.108954","DOIUrl":"10.1016/j.sse.2024.108954","url":null,"abstract":"<div><p>In this paper, we present a temperature and variability-aware Verilog-A-based compact model for simulating Ferroelectric FET. The model captures the rich physics of ferroelectric materials and the important electrical characteristics, such as the history effect, the impact of pulse width and amplitude on threshold voltage, and temperature-dependent degradation of polarization. The impact of variability is also explored regarding reliable operation of the FeFET. The developed model is robust and can accurately capture the experimentally observed trends, such as the change in polarization due to temperature, increased memory window on reading from the back-gate, etc. Further, we discuss two applications of our developed model viz. (a) multi-level-cell storage and (b) FeFET-based array for MAC operations. The designs are tested using the proposed model in commercial SPICE simulator at different temperatures including the effect of variation. Analysis presented in this article reveals that variability and temperature can be detrimental for operation of FeFET-based systems.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"218 ","pages":"Article 108954"},"PeriodicalIF":1.7,"publicationDate":"2024-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141051822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transient turn-on characteristics of Si RBDT and SiC MOSFET under nanosecond current pulse range","authors":"Zhengheng Qing,&nbsp;Lin Liang,&nbsp;Tong Liu","doi":"10.1016/j.sse.2024.108953","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108953","url":null,"abstract":"<div><p>With the development of pulse power supplies, solid-state semiconductor switches are required to have fast switching speeds and low losses. Both Reverse blocking diode thyristor (RBDT) and silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) have fast turn-on speed, making them suitable candidates for short pulse generator. In this paper, the transient turn-on characteristics of Si RBDT and SiC MOSFET are analyzed theoretically and validated experimentally. Si RBDT and commercial 1.2 kV/81A SiC MOSFET are comparatively investigated in switching current pulse with a rise time of several hundreds of nanoseconds. (1) The anode current of RBDT could rise exponentially because of the latch-up effect of Si RBDT, while the drain current of SiC MOSFET tends to be saturated. (2) Utilizing the current rise time (<em>T</em>_rise) to represent the switching speed, SiC MOSFET can switch faster when the current is lower than 400A. With the increase of the current, Si RBDT presents faster turn-on speed and lower switching loss due to the regenerative action of the two coupled transistors. (3) The transient characteristics of Si RBDT include a voltage-controlled inductance, while SiC MOSFET contains a current-controlled inductance based on the current rise time, respectively. With the increasing of the main voltage, the equivalent inductance of Si RBDT decreases and tends to be saturated when the main voltage is higher than half of the breakdown voltage of Si RBDT. For SiC MOSFET, the equivalent inductance increases until the drain current remains stable for a given gate voltage. This paper confirms the advantages of Si RBDT and SiC MOSFET in different situations.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108953"},"PeriodicalIF":1.7,"publicationDate":"2024-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140947999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hysteresis loops on voltage-current characteristics and optical responses of PEDOT:PSS/ZnO nanorods/ZnO:Ga heterostructure","authors":"Tomoaki Terasako ,&nbsp;Masakazu Yagi ,&nbsp;Tetsuya Yamamoto","doi":"10.1016/j.sse.2024.108955","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108955","url":null,"abstract":"<div><p>Volage (<em>V</em>)-current (<em>I</em>) curves of the poly (3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS)/ZnO nanorods (NRs)/ZnO:Ga (GZO) heterostructure exhibited a rectification behavior with hysteresis loops both in forward voltage (<em>V</em>_F) and reverse voltage (<em>V</em>_R) regions. The ultraviolet (UV) light irradiation of 360 nm led to the increase in the reverse current (<em>I</em>_R), i.e. generation of photocurrent (PC), and the decrease in the hysteresis loop area in the <em>V</em>_F region. In dark, the 1/<em>V</em> vs. ln (<em>I</em>/<em>V</em>²) plot revealed that the dominant carrier transport mechanisms in the low- and the high-<em>V</em>_F regions are the direct tunneling and the Fowler-Nordheim (F-N) tunneling through the dipole layer formed at the interface between the PEDOT:PSS and ZnO NRs layers, respectively. On the contrary, the carrier transport in the middle-<em>V</em>_F region in dark was dominated by the bulk-limited mechanisms, such as the space-charge-limited (SCL) conduction controlled by the single shallow traps, the trap-free SCL conduction, and the trap-filled-limit conduction controlled by the traps with Gaussian distribution. The UV light irradiation changed the carrier transport mechanism in the middle-<em>V</em>_F region to the trap-free SCL conduction. The resistive switching related to the hysteresis loop was found to be caused by the trapping and detrapping of the injected carriers at the traps. In dark, the maximum forward current was increased by the repetition of the <em>V</em>_F sweep of 0 V → 5 V → 0 V, but decreased by the repetition of the <em>V</em>_R sweep of 0 V → -5V → 0 V, indicating the possibility of the resistive memory. At the low <em>V</em>_Rs, PC spectra showed a main peak at 350 nm, which is corresponding to slightly higher photon energy than the bandgap energy of ZnO. Moreover, the existence of the tail extending into the bandgap was also observed on the PC spectra. From the time response of PC, the depth of the trap state was estimated to be 0.64–0.77 eV.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108955"},"PeriodicalIF":1.7,"publicationDate":"2024-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140951710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancement in electrical properties of dual-active-layer amorphous SiZnSnO/SiInZnO thin film transistors","authors":"Sandeep Kumar Maurya,&nbsp;Sang Yeol Lee","doi":"10.1016/j.sse.2024.108952","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108952","url":null,"abstract":"<div><p>Bi-layer thin film transistors (TFTs) have been fabricated with a channel structure comprising a dielectric layer, a semiconducting amorphous-Si-In-Zn-O (a-SIZO) layer, and a semiconducting amorphous-Si-Zn-Sn-O (a-SZTO) layer, aiming to improve field effect mobility and stability. These films were deposited using RF sputtering at room temperature. The TFTs with a bottom gate top contact, processed at 500 °C, exhibited high mobilities (<span><math><mrow><mo>&gt;</mo><mn>32</mn></mrow></math></span> cm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> V⁻¹ s⁻¹) along with a current on/off ratio of approximately 10<span><math><msup><mrow></mrow><mrow><mn>8</mn></mrow></msup></math></span> and a subthreshold swing (SS) value below 0.5 V decade⁻¹ primarily because of reduced trap density and presence of highly conducting ultrathin a-SIZO layer. Furthermore, the bi-layer TFTs demonstrated notable stability under negative and positive bias temperature stress conditions.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"218 ","pages":"Article 108952"},"PeriodicalIF":1.7,"publicationDate":"2024-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140950007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}