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A Schottky barrier field-effect transistor platform with variable Ge content on SOI SOI上可变锗含量的肖特基势垒场效应晶体管平台
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-23 DOI: 10.1016/j.sse.2025.109221
Andreas Fuchsberger , Lukas Wind , Aníbal Pacheco-Sanchez , Johannes Aberl , Moritz Brehm , Lilian Vogl , Peter Schweizer , Masiar Sistani , Walter M. Weber
{"title":"A Schottky barrier field-effect transistor platform with variable Ge content on SOI","authors":"Andreas Fuchsberger ,&nbsp;Lukas Wind ,&nbsp;Aníbal Pacheco-Sanchez ,&nbsp;Johannes Aberl ,&nbsp;Moritz Brehm ,&nbsp;Lilian Vogl ,&nbsp;Peter Schweizer ,&nbsp;Masiar Sistani ,&nbsp;Walter M. Weber","doi":"10.1016/j.sse.2025.109221","DOIUrl":"10.1016/j.sse.2025.109221","url":null,"abstract":"<div><div>Advancing SOI-based transistors with Ge-rich layers aims to increase device performance in terms of on-state operation and switching speed. Here, we investigate multi-heterojunction SiGe-based Schottky barrier FETs with Ge concentrations up to 75% by means of temperature- dependent electrical characterizations to identify the transport regimes and the effective barrier heights with a thermionic-emission-based model. Importantly, incorporating 33% Ge gives the best compromise for n- and p-type on-state symmetry. As the Ge concentration increases, the p-type on-state current becomes dominant, which is interesting for low-power p-type transistors.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109221"},"PeriodicalIF":1.4,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144908455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MULHACEN, enhanced multi-subband Monte Carlo simulator for nonplanar FETs 用于非平面场效应管的增强型多子带蒙特卡罗模拟器
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-23 DOI: 10.1016/j.sse.2025.109213
L. Donetti, C. Medina-Bailon, J.L. Padilla, C. Sampedro, F. Gamiz
{"title":"MULHACEN, enhanced multi-subband Monte Carlo simulator for nonplanar FETs","authors":"L. Donetti,&nbsp;C. Medina-Bailon,&nbsp;J.L. Padilla,&nbsp;C. Sampedro,&nbsp;F. Gamiz","doi":"10.1016/j.sse.2025.109213","DOIUrl":"10.1016/j.sse.2025.109213","url":null,"abstract":"<div><div>In this work, we present <span>Mulhacen</span>, a 3D multi-subband simulator developed for the accurate study of nonplanar devices which are at the core of present and future technology nodes. It allows to consider electrons in different conduction band valleys and, among its main features, we can highlight the accurate evaluation of quantum effects in the plane transverse to transport through the solution of the 2D Schrödinger equation in several device cross sections, as well as Monte Carlo description of transport. The simulator is based on a finite elements discretization, which allows an accurate description of realistic device geometries.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109213"},"PeriodicalIF":1.4,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144895147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Frequency-driven dielectric analysis of ultrathin HfOx-TiOx composite films 超薄HfOx-TiOx复合薄膜的频率驱动介电分析
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-22 DOI: 10.1016/j.sse.2025.109220
Rezwana Sultana , Karimul Islam , Piotr Jeżak , Robert Mroczyński
{"title":"Frequency-driven dielectric analysis of ultrathin HfOx-TiOx composite films","authors":"Rezwana Sultana ,&nbsp;Karimul Islam ,&nbsp;Piotr Jeżak ,&nbsp;Robert Mroczyński","doi":"10.1016/j.sse.2025.109220","DOIUrl":"10.1016/j.sse.2025.109220","url":null,"abstract":"<div><div>This study investigates the frequency-dependent dielectric properties of ultrathin HfO<sub>x</sub>-TiO<sub>x</sub> composite films (HTO) in a metal–oxide–semiconductor (MOS) configuration over a frequency range of 1 kHz to 3 MHz. The films were deposited using a pulsed-DC magnetron sputtering technique in an atomic layer deposition-like manner, incorporating very thin TiO<sub>x</sub> layers within the bulk of HfO<sub>x</sub>. Structural analysis revealed that the films are amorphous and exhibit uniform and smooth surfaces. The dielectric constant (<em>ε</em>′) and dielectric loss (<em>ε</em>′′) exhibit a decreasing trend with increasing frequency, demonstrating typical dielectric behavior. Furthermore, the characteristic dielectric relaxation frequency shifts toward lower frequency values with the insertion of TiO<sub>x</sub>. The Cole-Cole plot confirms the non-Debye relaxation behavior across all samples. Optical spectroscopy analysis reveals a systematic increase in the optical band gap upon more TiO<sub>x</sub> insertion. Analysis of current–voltage (I-V) characteristics demonstrates low leakage currents across the composite films. Understanding the dielectric parameters and the electrical characteristics is crucial for the potential application of these films in advanced electronic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109220"},"PeriodicalIF":1.4,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144908456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Geometrical variability impact on the gate tunneling leakage mechanisms in FinFETs 几何变异性对栅极隧穿泄漏机制的影响
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-20 DOI: 10.1016/j.sse.2025.109212
C. Medina-Bailon, J.L. Padilla, L. Donetti, C. Navarro, C. Sampedro, F. Gamiz
{"title":"Geometrical variability impact on the gate tunneling leakage mechanisms in FinFETs","authors":"C. Medina-Bailon,&nbsp;J.L. Padilla,&nbsp;L. Donetti,&nbsp;C. Navarro,&nbsp;C. Sampedro,&nbsp;F. Gamiz","doi":"10.1016/j.sse.2025.109212","DOIUrl":"10.1016/j.sse.2025.109212","url":null,"abstract":"<div><div>Given the critical role that quantum tunneling effects play in the behavior of nanoelectronic devices, it is essential to investigate the influence and restraints of these phenomena on the overall transistor performance. In this work, a previously developed gate leakage model, incorporated into an in-house 2D Multi-Subband Ensemble Monte Carlo simulation framework, is employed to analyze the leakage current flowing across the gate insulator. The primary objective is to evaluate how variations in key geometrical parameters (specifically, gate oxide and semiconductor thicknesses dimensions) affect the magnitude and bias dependence of tunneling-induced leakage. Simulations are performed on a representative FinFET structure, and the results reveal that tunneling effects become increasingly pronounced at low gate voltages in devices with thinner oxides and thicker semiconductor thickness. These findings underscore the relevance of incorporating quantum tunneling mechanisms in predictive modeling of advanced transistor architectures.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109212"},"PeriodicalIF":1.4,"publicationDate":"2025-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145118356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An All-GaN cascode device with integrated plane-parallel capacitor with high dynamic breakdown voltage and high switching performance 一种具有高动态击穿电压和高开关性能的集成平面并联电容器的全氮化镓级联器件
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-19 DOI: 10.1016/j.sse.2025.109219
Jinyi Wang , Yian Yin , Qiao Sun , Chunxiao Zhao , Qian Zeng , Jiahao Du , Yele Qu , Tiankai Wang , Nan Jiang
{"title":"An All-GaN cascode device with integrated plane-parallel capacitor with high dynamic breakdown voltage and high switching performance","authors":"Jinyi Wang ,&nbsp;Yian Yin ,&nbsp;Qiao Sun ,&nbsp;Chunxiao Zhao ,&nbsp;Qian Zeng ,&nbsp;Jiahao Du ,&nbsp;Yele Qu ,&nbsp;Tiankai Wang ,&nbsp;Nan Jiang","doi":"10.1016/j.sse.2025.109219","DOIUrl":"10.1016/j.sse.2025.109219","url":null,"abstract":"<div><div>All-GaN Cascode devices have been shown to have higher switching speeds than standalone E-mode devices. However, during the switching process of the device, the breakdown voltage drops significantly, this will greatly reduce the reliability of the device, especially in the presence of voltage overshoot. In this paper, an All-GaN Cascode structure with integrated plane-parallel capacitor structure is proposed, and the breakdown voltage in the switching process is referred to as the dynamic breakdown voltage. The test results show that the dynamic breakdown voltage is increased from 497 V to 639 V compared with the conventional structure. In addition, a dual-pulse test circuit is set up to test the switching performance of All-GaN Cascode devices under different conditions, it is proved that the series structure of All-GaN Cascode device can reduce the deterioration of switching performance caused by the increase of capacitance. The above results indicate that All-GaN Cascode devices may have great application potential in high speed and high voltage switching circuits.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109219"},"PeriodicalIF":1.4,"publicationDate":"2025-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144893113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nanoscale SOI strain engineering: STRASS-enabled local stress optimization 纳米尺度SOI应变工程：strass支持的局部应力优化
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-18 DOI: 10.1016/j.sse.2025.109215
L.D. Mohgouk Zouknak, V-H. Le, N-P. Tran, F. Milesi, J.-M. Hartmann, S. Jarjayes, J. Lespiaux, A. Jannaud, F. Aussenac, N. Bernier, Ph. Rodriguez, L. Brunet, B. Duriez, M.C. Cyrille, C. Fenouillet-Beranger
{"title":"Nanoscale SOI strain engineering: STRASS-enabled local stress optimization","authors":"L.D. Mohgouk Zouknak,&nbsp;V-H. Le,&nbsp;N-P. Tran,&nbsp;F. Milesi,&nbsp;J.-M. Hartmann,&nbsp;S. Jarjayes,&nbsp;J. Lespiaux,&nbsp;A. Jannaud,&nbsp;F. Aussenac,&nbsp;N. Bernier,&nbsp;Ph. Rodriguez,&nbsp;L. Brunet,&nbsp;B. Duriez,&nbsp;M.C. Cyrille,&nbsp;C. Fenouillet-Beranger","doi":"10.1016/j.sse.2025.109215","DOIUrl":"10.1016/j.sse.2025.109215","url":null,"abstract":"<div><div>As device dimensions continue to shrink, improving electrical performance has become a major challenge in realizing the next generation of FDSOI transistors. One of the key strategies to improve electrical performance is to introduce mechanical stress into the transistor channel to increase carrier mobility. We have investigated two strategies for achieving localized strain using the STRASS process. We have also compared the effectiveness of these approaches, focusing on (i) strain relaxation as device dimensions are reduced and (ii) the effect of Si<sub>0.7</sub>Ge<sub>0.3</sub> layer thickness on the resulting stress. We have demonstrated uniaxial stresses <span><math><mrow><msub><mi>σ</mi><mrow><mi>xx</mi></mrow></msub></mrow></math></span> &gt; 0.8 GPa in active-like structures with W = 130 nm width.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109215"},"PeriodicalIF":1.4,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144893114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fracture dynamics in Smart Cut™ technology: Wafer deformation measurement 智能切割™技术中的断裂动力学：晶圆变形测量
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-17 DOI: 10.1016/j.sse.2025.109218
L. Colonel , K. Blanco , S. Tardif , P.E. Acosta Alba , F. Mazen , J. Eymery , D. Landru , F. Rieutord
{"title":"Fracture dynamics in Smart Cut™ technology: Wafer deformation measurement","authors":"L. Colonel ,&nbsp;K. Blanco ,&nbsp;S. Tardif ,&nbsp;P.E. Acosta Alba ,&nbsp;F. Mazen ,&nbsp;J. Eymery ,&nbsp;D. Landru ,&nbsp;F. Rieutord","doi":"10.1016/j.sse.2025.109218","DOIUrl":"10.1016/j.sse.2025.109218","url":null,"abstract":"<div><div>High-Speed Cameras help in characterizing the splitting step in the Smart Cut™ technology. Full wafer-scale deformation monitoring upon annealing is then possible. This paper describes the setup, equipment and methodology used to estimate the backside wafer deformation and curvature upon fracture propagation in situ during the fracture step. Finally, with such a setup, the fracture process of a SOI-ready structure is studied dynamically over the whole propagation time scale. These results are consistent with literature work performed using punctual measurements methods and will allow in the future to emphasize the effect of process’ and structure’s geometry.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109218"},"PeriodicalIF":1.4,"publicationDate":"2025-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144879308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Behavioral SPICE model for memristive crosspoint arrays operating in the nonlinear transport regime 非线性输运状态下记忆交点阵列的行为SPICE模型
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-15 DOI: 10.1016/j.sse.2025.109214
X. Pérez , R. Picos , J. Suñé , E. Miranda
{"title":"Behavioral SPICE model for memristive crosspoint arrays operating in the nonlinear transport regime","authors":"X. Pérez ,&nbsp;R. Picos ,&nbsp;J. Suñé ,&nbsp;E. Miranda","doi":"10.1016/j.sse.2025.109214","DOIUrl":"10.1016/j.sse.2025.109214","url":null,"abstract":"<div><div>In this letter, a fully behavioral SPICE model for <em>M</em> × <em>N</em> memristive crosspoint arrays (CPAs) is presented. The proposed approach incorporates the current–voltage characteristics of the memdiode model for resistive switching devices, which can account for both the linear (low-voltage) and nonlinear (high-voltage) transport regimes of memristors. At low voltages, the model coincides with the conventional linear formulation based on matrix–vector multiplication (MVM) method. At high voltages, however, this algebraic operation is no longer valid. The model supports two operation modes depending on the requirements of the surrounding circuitry: voltage-controlled current source (VCCS) and voltage-controlled voltage source (VCVS). Current-controlled modes are also feasible for specific applications. Basic guidelines for applying these different modes are provided.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109214"},"PeriodicalIF":1.4,"publicationDate":"2025-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144867289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation of hole spin qubits in SOI quantum dots: Comparison between different geometries SOI量子点中空穴自旋量子比特的模拟：不同几何形状的比较
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-14 DOI: 10.1016/j.sse.2025.109201
Lorenzo Raschi, Antonio Gnudi
{"title":"Simulation of hole spin qubits in SOI quantum dots: Comparison between different geometries","authors":"Lorenzo Raschi,&nbsp;Antonio Gnudi","doi":"10.1016/j.sse.2025.109201","DOIUrl":"10.1016/j.sse.2025.109201","url":null,"abstract":"<div><div>Hole spins in semiconductor quantum dots are a promising path to implement electrically controlled qubits. This work compares different geometries of hole spin qubits implemented in SOI quantum dots with different nanowire orientations. The goal is to optimize geometry and nanowire orientation to maximize the Rabi frequency for a given RF drive amplitude, based on the theory in Venitucci et al. (2018). The hole eigenfunctions are calculated using the <span><math><mrow><mi>k</mi><mi>⋅</mi><mi>p</mi></mrow></math></span> model within a COMSOL-based framework. The <span><math><mi>g</mi></math></span>-matrix formalism is exploited to compute Rabi frequency as a function of the magnetic field orientation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109201"},"PeriodicalIF":1.4,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144885394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Numerical investigation of effect of Si separator in bottom dielectric isolation forksheet FETs via in-house TCAD process emulator and device simulator 利用TCAD过程仿真器和器件仿真器对底部介质隔离叉片场效应管中硅分离器的影响进行了数值研究
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-08-13 DOI: 10.1016/j.sse.2025.109211
In Ki Kim, Sung-Min Hong
{"title":"Numerical investigation of effect of Si separator in bottom dielectric isolation forksheet FETs via in-house TCAD process emulator and device simulator","authors":"In Ki Kim,&nbsp;Sung-Min Hong","doi":"10.1016/j.sse.2025.109211","DOIUrl":"10.1016/j.sse.2025.109211","url":null,"abstract":"<div><div>In this work, we investigate the effect of a Si separator on the fabrication and performance of a bottom dielectric isolation (BDI) forksheet field-effect transistor (FSFET) using our in-house technology computer-aided design process emulator and device simulator. The process emulator is implemented with a three-dimensional multi-level-set method to emulate the BDI FSFET fabrication under various process conditions. Our results demonstrate that the addition of a Si separator is a plausible option for the BDI FSFET. To verify this conclusion from an electrical performance perspective, we simulate the electrical characteristics of the devices using our in-house device simulator. The device structures generated from the process emulator are directly used for the device simulation. The device simulation results confirm that incorporating a Si separator remains the optimal choice, even when considering the device performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109211"},"PeriodicalIF":1.4,"publicationDate":"2025-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144851772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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