{"title":"利用TCAD过程仿真器和器件仿真器对底部介质隔离叉片场效应管中硅分离器的影响进行了数值研究","authors":"In Ki Kim, Sung-Min Hong","doi":"10.1016/j.sse.2025.109211","DOIUrl":null,"url":null,"abstract":"<div><div>In this work, we investigate the effect of a Si separator on the fabrication and performance of a bottom dielectric isolation (BDI) forksheet field-effect transistor (FSFET) using our in-house technology computer-aided design process emulator and device simulator. The process emulator is implemented with a three-dimensional multi-level-set method to emulate the BDI FSFET fabrication under various process conditions. Our results demonstrate that the addition of a Si separator is a plausible option for the BDI FSFET. To verify this conclusion from an electrical performance perspective, we simulate the electrical characteristics of the devices using our in-house device simulator. The device structures generated from the process emulator are directly used for the device simulation. The device simulation results confirm that incorporating a Si separator remains the optimal choice, even when considering the device performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109211"},"PeriodicalIF":1.4000,"publicationDate":"2025-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Numerical investigation of effect of Si separator in bottom dielectric isolation forksheet FETs via in-house TCAD process emulator and device simulator\",\"authors\":\"In Ki Kim, Sung-Min Hong\",\"doi\":\"10.1016/j.sse.2025.109211\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>In this work, we investigate the effect of a Si separator on the fabrication and performance of a bottom dielectric isolation (BDI) forksheet field-effect transistor (FSFET) using our in-house technology computer-aided design process emulator and device simulator. The process emulator is implemented with a three-dimensional multi-level-set method to emulate the BDI FSFET fabrication under various process conditions. Our results demonstrate that the addition of a Si separator is a plausible option for the BDI FSFET. To verify this conclusion from an electrical performance perspective, we simulate the electrical characteristics of the devices using our in-house device simulator. The device structures generated from the process emulator are directly used for the device simulation. The device simulation results confirm that incorporating a Si separator remains the optimal choice, even when considering the device performance.</div></div>\",\"PeriodicalId\":21909,\"journal\":{\"name\":\"Solid-state Electronics\",\"volume\":\"229 \",\"pages\":\"Article 109211\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-08-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid-state Electronics\",\"FirstCategoryId\":\"101\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S003811012500156X\",\"RegionNum\":4,\"RegionCategory\":\"物理与天体物理\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S003811012500156X","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Numerical investigation of effect of Si separator in bottom dielectric isolation forksheet FETs via in-house TCAD process emulator and device simulator
In this work, we investigate the effect of a Si separator on the fabrication and performance of a bottom dielectric isolation (BDI) forksheet field-effect transistor (FSFET) using our in-house technology computer-aided design process emulator and device simulator. The process emulator is implemented with a three-dimensional multi-level-set method to emulate the BDI FSFET fabrication under various process conditions. Our results demonstrate that the addition of a Si separator is a plausible option for the BDI FSFET. To verify this conclusion from an electrical performance perspective, we simulate the electrical characteristics of the devices using our in-house device simulator. The device structures generated from the process emulator are directly used for the device simulation. The device simulation results confirm that incorporating a Si separator remains the optimal choice, even when considering the device performance.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.