纳米尺度SOI应变工程：strass支持的局部应力优化

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-08-18 DOI:10.1016/j.sse.2025.109215

L.D. Mohgouk Zouknak, V-H. Le, N-P. Tran, F. Milesi, J.-M. Hartmann, S. Jarjayes, J. Lespiaux, A. Jannaud, F. Aussenac, N. Bernier, Ph. Rodriguez, L. Brunet, B. Duriez, M.C. Cyrille, C. Fenouillet-Beranger

{"title":"纳米尺度SOI应变工程：strass支持的局部应力优化","authors":"L.D. Mohgouk Zouknak, V-H. Le, N-P. Tran, F. Milesi, J.-M. Hartmann, S. Jarjayes, J. Lespiaux, A. Jannaud, F. Aussenac, N. Bernier, Ph. Rodriguez, L. Brunet, B. Duriez, M.C. Cyrille, C. Fenouillet-Beranger","doi":"10.1016/j.sse.2025.109215","DOIUrl":null,"url":null,"abstract":"<div><div>As device dimensions continue to shrink, improving electrical performance has become a major challenge in realizing the next generation of FDSOI transistors. One of the key strategies to improve electrical performance is to introduce mechanical stress into the transistor channel to increase carrier mobility. We have investigated two strategies for achieving localized strain using the STRASS process. We have also compared the effectiveness of these approaches, focusing on (i) strain relaxation as device dimensions are reduced and (ii) the effect of Si<sub>0.7</sub>Ge<sub>0.3</sub> layer thickness on the resulting stress. We have demonstrated uniaxial stresses <span><math><mrow><msub><mi>σ</mi><mrow><mi>xx</mi></mrow></msub></mrow></math></span> > 0.8 GPa in active-like structures with W = 130 nm width.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109215"},"PeriodicalIF":1.4000,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Nanoscale SOI strain engineering: STRASS-enabled local stress optimization\",\"authors\":\"L.D. Mohgouk Zouknak, V-H. Le, N-P. Tran, F. Milesi, J.-M. Hartmann, S. Jarjayes, J. Lespiaux, A. Jannaud, F. Aussenac, N. Bernier, Ph. Rodriguez, L. Brunet, B. Duriez, M.C. Cyrille, C. Fenouillet-Beranger\",\"doi\":\"10.1016/j.sse.2025.109215\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>As device dimensions continue to shrink, improving electrical performance has become a major challenge in realizing the next generation of FDSOI transistors. One of the key strategies to improve electrical performance is to introduce mechanical stress into the transistor channel to increase carrier mobility. We have investigated two strategies for achieving localized strain using the STRASS process. We have also compared the effectiveness of these approaches, focusing on (i) strain relaxation as device dimensions are reduced and (ii) the effect of Si<sub>0.7</sub>Ge<sub>0.3</sub> layer thickness on the resulting stress. We have demonstrated uniaxial stresses <span><math><mrow><msub><mi>σ</mi><mrow><mi>xx</mi></mrow></msub></mrow></math></span> > 0.8 GPa in active-like structures with W = 130 nm width.</div></div>\",\"PeriodicalId\":21909,\"journal\":{\"name\":\"Solid-state Electronics\",\"volume\":\"229 \",\"pages\":\"Article 109215\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-08-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid-state Electronics\",\"FirstCategoryId\":\"101\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0038110125001601\",\"RegionNum\":4,\"RegionCategory\":\"物理与天体物理\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125001601","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

随着器件尺寸的不断缩小，提高电性能已成为实现下一代FDSOI晶体管的主要挑战。提高电性能的关键策略之一是在晶体管通道中引入机械应力以增加载流子迁移率。我们研究了利用STRASS工艺实现局部应变的两种策略。我们还比较了这些方法的有效性，重点关注(i)器件尺寸减小时的应变松弛以及（ii） Si0.7Ge0.3层厚度对产生应力的影响。我们在W = 130 nm宽的类活性结构中发现了单轴应力σxx >； 0.8 GPa。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Nanoscale SOI strain engineering: STRASS-enabled local stress optimization

As device dimensions continue to shrink, improving electrical performance has become a major challenge in realizing the next generation of FDSOI transistors. One of the key strategies to improve electrical performance is to introduce mechanical stress into the transistor channel to increase carrier mobility. We have investigated two strategies for achieving localized strain using the STRASS process. We have also compared the effectiveness of these approaches, focusing on (i) strain relaxation as device dimensions are reduced and (ii) the effect of Si_0.7Ge_0.3 layer thickness on the resulting stress. We have demonstrated uniaxial stresses

σ_{xx}

> 0.8 GPa in active-like structures with W = 130 nm width.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.