Integration of W vias for individual coupling control in 28 nm FD-SOI qubit arrays

Using known industrial fabrication methods, we repurpose W vias and, with a single contact patterning step, integrate both gates to define the electrochemical potential of quantum dots (QDs) and vias to define their coupling barriers in CMOS-based, linear qubit arrays. We show both simulated and experimental results of individual coupling control of QDs in arrays that were fully fabricated in a foundry on the 28 nm FD-SOI platform. We show detailed wafer-level transfer characteristics for each barrier implemented on a 1x3 linear array, at room temperature and at 2 K, which demonstrate that the vias are well-behaved MOSFET gates with electrostatic control over the Si channel.