Experimental investigation of 7-level stacked nanosheet nMOSFETs for high-temperature applications

This study experimentally investigates the electrical characteristics of seven-level stacked nanosheet SOI nMOSFETs for high-temperature applications. The experimental findings reveal a significant advantage of this architecture, demonstrating a reduced threshold voltage variation with temperature compared to both two-level stacked nanosheet transistors and state-of-the-art Fully-Depleted SOI MOSFETs. Furthermore, analysis of the normalized transconductance per total width indicates that the enhancement in carrier mobility, typically observed for wider nanosheets relative to narrower ones, tends to saturate for wider devices and to reduce as the operating temperature increases. Also, the normalized transconductance per channel length indicates a reduction of mobility for short-channel devices.