Analysis of operation delay and switching speed limitation due to source/drain resistance and subgap density of states in amorphous InGaZnOx/HfZrOx ferroelectric thin-film transistor

In recent years, ferroelectric memory has garnered significant attention as a next-generation non-volatile memory capable of operating at a low voltage and high speed, making it suitable for embedded memory and in-memory computing applications. Previous research has extensively focused on optimizing the polarization switching speed and operational characteristics of ferroelectric thin films themselves. Recent studies have also demonstrated experimental implementations of memory devices utilizing various semiconductors beyond silicon channels. However, to effectively apply and evaluate ferroelectrics at the transistor level for memory applications, it is crucial to consider not only the intrinsic properties of ferroelectric materials but also to integrate and analyze the performance characteristics of transistors. The size of ferroelectric field effect transistors (FeFET) and the characteristics of semiconductor channel material can significantly influence memory performance and operational speed. Differences in performance may arise depending on the semiconductor channel employed and how defects respond within the materials other than ferroelectric film.

In this study, ferroelectric thin-film transistors (FeTFTs) and corresponding test element group (TEG) with an amorphous InGaZnO_x (a-IGZO) channel and HfZrO_x (HZO) ferroelectric insulator were fabricated and analyzed to investigate the correlation between operational speed and semiconductor channel properties. Measurements, including DC transfer curves, gate capacitance versus gate voltage (C_GDS–V_G) curves, and the frequency dispersion of C_GDS, were conducted. The results confirmed potential limitations in operational speed due to a-IGZO channel characteristics. TCAD simulations were calibrated considering the extracted subgap density of states (DOS) and contact serial resistance, revealing that the speed of FeTFTs can be constrained by serial resistance and defect responses. These findings underscore the necessity of selecting appropriate device structures and materials for effectively evaluating FeTFTs, and highlight the complexities involved in assessing ferroelectric memory performance, emphasizing the interplay between ferroelectric films and semiconductor channels, interface charges, defect levels influenced by processes, and inherent semiconductor channel performance. This research provides insights into the comprehensive analysis required for evaluating ferroelectric memory devices effectively.