Jaejoong Jeong , Youngkeun Park , Hwanuk Guim , Yongku Baek , Heetae Kim , Dongbin Kim , Hui Jae Cho , Su-hyeon Gwon , Min Ju Kim , Byung Jin Cho
{"title":"Selective grain size enlargement in Contact/Via plugs using Nanosecond green laser annealing","authors":"Jaejoong Jeong , Youngkeun Park , Hwanuk Guim , Yongku Baek , Heetae Kim , Dongbin Kim , Hui Jae Cho , Su-hyeon Gwon , Min Ju Kim , Byung Jin Cho","doi":"10.1016/j.sse.2025.109098","DOIUrl":"10.1016/j.sse.2025.109098","url":null,"abstract":"<div><div>The rapid decrease in interconnect Critical Dimensions (CDs) within logic devices and growth in the contact height of 3D memory devices have led to increased contact/via plugs resistance. In this study, we introduce an approach to reduce the resistance of the contact/via plugs by engineering the grain size of the plugs using Nanosecond Green Laser Annealing (NGLA) with a low energy fluence (= 0.1 J/cm<sup>2</sup>). Because of the proximity between adjacent W plugs, diffraction of the laser light can occur which will help the laser energy to be absorbed by the sidewall of the W plugs. In addition, the difference in reflectivity between the plug region and W interconnect lines can cause grain size enlargement to selectively occur in the plug region. The NGLA process increased grain size in the plugs up to 79.9 %, resulting as much as a 26 % reduction in tungsten plug resistance. The standard deviation of the plug resistance was also improved from 14.6 % to 7.9 % after the NGLA process.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109098"},"PeriodicalIF":1.4,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Q. Chen , L.Van Brandt , V. Kilchytska , E. Bestelink , R.A. Sporea , D. Flandre
{"title":"Low-frequency noise in polysilicon Source-Gated Thin-Film transistors","authors":"Q. Chen , L.Van Brandt , V. Kilchytska , E. Bestelink , R.A. Sporea , D. Flandre","doi":"10.1016/j.sse.2025.109099","DOIUrl":"10.1016/j.sse.2025.109099","url":null,"abstract":"<div><div>The low-frequency noise (LFN) of thin-film polysilicon source-gated transistors (SGTs) is investigated. DC characteristics were firstly measured and typical behaviors of SGT were observed. Then, TCAD simulations were performed with different doping concentrations. Current density distribution shows that the variation of the conduction channel position in the thin film induces a second plateau in the (<em>g</em><sub>m</sub>/<em>I</em><sub>D</sub>)<sup>2</sup> curves for bias points in subthreshold region. LFN was measured for both SGTs and thin-film field-effect transistor (TFTs) configurations. 1/<em>f</em> noise is confirmed as the main component of LFN in all our measurements. Carrier mobility fluctuation (CMF) is found to dominate the origin of LFN in TFT configuration and the low-current region of SGT. In the high-current region of SGT measurements, 1/<em>f</em> noise is mainly attributed to carrier number fluctuation (CNF).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109099"},"PeriodicalIF":1.4,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143641913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-endurance bulk CMOS one-transistor cryo-memory","authors":"A. Zaslavsky , P.R. Shrestha , V.Ortiz Jimenez , J.P. Campbell , C.A. Richter","doi":"10.1016/j.sse.2025.109097","DOIUrl":"10.1016/j.sse.2025.109097","url":null,"abstract":"<div><div>Previously we reported a compact one-transistor (1 T) 180 nm bulk CMOS cryo-memory with a high ≈10<sup>7</sup> <em>I</em><sub>1</sub>/<em>I</em><sub>0</sub> memory window and long ≈800 s retention time based on impact-ionization-induced charging of the transistor body. Here, we present the endurance and retention characteristics of our 1 T memory obtained from high-speed measurements at <em>T</em> = 7 K. We observe excellent endurance, with no visible degradation over 10<sup>9</sup> write ‘1′/write ‘0′ cycles. The measured retention time varies with the memory window and the leakage current, but it exceeds 10 s for a 30X <em>I</em><sub>1</sub>/<em>I</em><sub>0</sub> memory window and would be even higher in a device with no substrate contact.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109097"},"PeriodicalIF":1.4,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143563058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jung Rae Cho , Jingyu Park , Seung Joo Myoung , Tae Jun Yang , Changwook Kim , Jong-Ho Bae , Sung-Jin Choi , Dong Myong Kim , Ickhyun Song , Dae Hwan Kim
{"title":"Investigation of reconfigurable logic gate using integrated amorphous InGaZnO ReRAM and thin-film transistor","authors":"Jung Rae Cho , Jingyu Park , Seung Joo Myoung , Tae Jun Yang , Changwook Kim , Jong-Ho Bae , Sung-Jin Choi , Dong Myong Kim , Ickhyun Song , Dae Hwan Kim","doi":"10.1016/j.sse.2025.109084","DOIUrl":"10.1016/j.sse.2025.109084","url":null,"abstract":"<div><div>This paper proposes a new reconfigurable logic circuits based on InGaZnO resistive random-access memory (ReRAM) and presents a comprehensive investigation of their electrical characteristics and logic operation. Two fundamental equations that govern the transport mechanism of oxygen ions were utilized to model the formation of lateral and vertical conducting filaments in ReRAM devices in a circuit simulation environment. Based on the device models, the electrical behavior of ReRAM was examined and verified, using circuit simulators. Experimental results from dc current–voltage and pulse measurements of ReRAM and thin-film transistors (TFTs) demonstrate their electrical switching characteristics. The paper analyzes and validates the operation of two ReRAM-based logic configurations: 1 T-1 M (one transistor and one ReRAM cell) and 2 T-2 M−INV (inverter). A detailed analysis were conducted to compare the proposed ReRAM-based logic with the conventional CMOS counterparts, revealing favorable advantages in reducing transistor counts and die areas. The 1 T-1 M and 2 T-2 M−INV exhibit reconfigurable logic operations under different resistive states of ReRAM cells. Additionally, the investigations of short-circuit current profiles shows the superior performance of ReRAM-based logic gates to the CMOS counterpart in terms of power consumption. Overall, this study investigates the feasibility of ReRAM-based reconfigurable logic circuits for future low-power and high-performance computing applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109084"},"PeriodicalIF":1.4,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143487699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Minqiang Liu , Xuqiang Liu , Guoping Xiao , Bobo Wang , Sanyong Zou , Le Zhong , Xianguo Xu , Chao Zeng , Shuyi Zhang , Guanghai Tang , Fang Deng , Abuduwayiti Aierken
{"title":"Comparison of radiation effects of LM and UMM structure GaAs triple-junction solar cells under 1 MeV neutron irradiation","authors":"Minqiang Liu , Xuqiang Liu , Guoping Xiao , Bobo Wang , Sanyong Zou , Le Zhong , Xianguo Xu , Chao Zeng , Shuyi Zhang , Guanghai Tang , Fang Deng , Abuduwayiti Aierken","doi":"10.1016/j.sse.2025.109087","DOIUrl":"10.1016/j.sse.2025.109087","url":null,"abstract":"<div><div>The output performances of lattice-matched (LM) and upright metamorphic (UMM) GaAs triple-junction solar cells under 1 MeV neutron irradiation were studied. The results show that the electrical performance, including open-circuit voltage, short-circuit current, maximum output power and fill factor of the solar cells were degraded seriously with the increase of neutron irradiation fluence. Meanwhile, the series resistance and the shunt resistance of solar cells are increased and decreased, respectively, when the neutron irradiation fluence increased. The degradation of maximum output power in LM and UMM GaAs cells is about the same level of 72.9 % and 72.3 % of its initial values, respectively, when the irradiation fluence is reached 6 × 10<sup>12</sup> n/cm<sup>2</sup>. By comparing the integrated current densities, it was found out that the current-limiting subcell in LM cells s always GaAs middle cell, and in the UMM cell, the current limiting unit is changed from GaInP top subcell to GaInAs middle subcell after high fluence neutron irradiation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109087"},"PeriodicalIF":1.4,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143437754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Influence of temperature inhomogeneity and trap charge on current imbalance of SiC MOSFETs","authors":"Chunsheng Guo, Jiapeng Li, Yamin Zhang, Hui Zhu, Meng Zhang, Shiwei Feng","doi":"10.1016/j.sse.2025.109085","DOIUrl":"10.1016/j.sse.2025.109085","url":null,"abstract":"<div><div>For SiC MOSFETs, either multi-chip modules or multiple discrete devices need to be connected in parallel to achieve high current capacities. However, the current imbalance that occurs in parallel applications can reduce device reliability. This paper focused on the effects of both temperature inhomogeneity and gate trap charge on the current imbalance behavior of SiC MOSFETs, and it also presented a comparison study of the effects of threshold voltage differences on the current inhomogeneity. Finally, the effects of the three factors above on the current inhomogeneity characteristics of SiC MOSFETs were compared in terms of their voltage and time dimensions. The results show that the percentage of the drain-source current imbalance due to temperature inhomogeneity for static processes can be maintained consistently at more than 10%. For dynamic processes, the percentage of the drain-source current imbalance due to temperature inhomogeneity can similarly exceed 10%.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109085"},"PeriodicalIF":1.4,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143437723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jingwen Chen , Fucheng Wang , Zhong Pan , Jang-Kun Song , Yong-Sang Kim , Muhammad Quddamah Khokhar , Junsin Yi
{"title":"Improvement of charge storage and retention characteristics of HfO2 Charge-Trapping layer in NVM based on InGaZnO channels","authors":"Jingwen Chen , Fucheng Wang , Zhong Pan , Jang-Kun Song , Yong-Sang Kim , Muhammad Quddamah Khokhar , Junsin Yi","doi":"10.1016/j.sse.2025.109077","DOIUrl":"10.1016/j.sse.2025.109077","url":null,"abstract":"<div><div>In recent years, with the widespread application of semiconductor thin-film memory devices, the focus of research has gradually shifted to how to fabricate memory with larger storage windows and longer retention times. This study employs the rapid thermal annealing (RTA) method to conduct multiple annealing treatments on charge trapping memory (CTM) devices that use HfO<sub>2</sub> as the charge trapping layer, the leakage current of the device is reduced, and the negative deviation of threshold voltage is improved. During the experiments, the charge trapping layer (CTL) and tunneling layer (TL) of the devices were deposited, and a 50 nm IGZO thin film was deposited as the channel layer. The study investigates the memory performance of TFT-NVM (thin film transistor non-volatile memory) after RTA under different conditions. The results showed that the TFT-NVM with the Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>/SiO<sub>2</sub> structure has a large memory window (1.4 V) and good charge retention (>71.39 %) before O<sub>2</sub> annealing treatment. This provides a feasible approach for future research on TFT-NVM.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109077"},"PeriodicalIF":1.4,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143437724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chia-Lung Hung , Yi-Kai Hsiao , Jing-Neng Yao , Hao-Chung Kuo
{"title":"Well-balanced 4H-SiC JBSFET: Integrating JBS diode and VDMOSFET characteristics for reliable 1700V applications","authors":"Chia-Lung Hung , Yi-Kai Hsiao , Jing-Neng Yao , Hao-Chung Kuo","doi":"10.1016/j.sse.2025.109083","DOIUrl":"10.1016/j.sse.2025.109083","url":null,"abstract":"<div><div>SiC power devices are suitable for high voltage and temperature applications due to their higher breakdown electrical field and thermal conductivity. Recently, many SiC SBDs and VDMOSFETs have been commercially produced. In comparison to Si-IGBT devices, the inherent body diode of SiC VDMOSFETs can also be used as the freewheeling diode in inductive switching power circuits, eliminating the need for an additional packaged diode. This can save costs and reduce the footprint of the total package. However, the bipolar carrier conduction and minority carrier injection mechanism on the body diode of SiC VDMOSFETs result in a higher turn-on knee voltage and longer reverse recovery time when used as a freewheeling diode. In fact, SiC SBDs are often utilized to replace the body diode, aiming to enhance the knee voltage and reverse recovery speed. To harness both the benefits of SiC VDMOSFETs and SBDs, it is worthwhile to integrate these two types of power devices into a single monolithic chip. In this study, we fabricated integrated JBS diodes into VDMOSFETs (JBSFETs) targeting 1700 V applications. Well-behaved JBSFETs with a threshold voltage (V<sub>th</sub>) of 1.9 V, specific on-resistance (R<sub>on,sp</sub>) of 5.2 mΩ-cm<sup>2</sup>, and acceptable blocking voltage (BV) of 2373 V have been achieved. The temperature dependence of the JBSFET device characteristics was also investigated. These results represent significant progress in implementing high-performance JBSFETs in power electronics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109083"},"PeriodicalIF":1.4,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yongjia Li , Di Gui , Feilu Chen , Wangran Wu , Weifeng Sun
{"title":"Impacts of trench angle on the performance of trench super-junction vertical double-diffused metal-oxide-semiconductor","authors":"Yongjia Li , Di Gui , Feilu Chen , Wangran Wu , Weifeng Sun","doi":"10.1016/j.sse.2025.109086","DOIUrl":"10.1016/j.sse.2025.109086","url":null,"abstract":"<div><div>In this paper, the electrical properties of the 600-V and 800-V super-junction (SJ) vertical double-diffused metal-oxide-semiconductor (VDMOS) with a non-vertical trench were examined thoroughly. The analytical model containing the trench angle was developed for SJ VDMOS with the full depletion (FD) working mode, confirmed by the experimental results and TCAD simulations. For the devices with the non-full depletion (NFD) working mode, impacts of trench angle on the electrical properties were studied by TCAD simulations. It is found that, for SJ VDMOSs with both FD mode and NFD mode, the trench angle of 89.8° accounts for the best device performance. Compared with the SJ VDMOS with the vertical trench, the device with the trench angle of 89.8° has 25 % lower minimum on-resistance and 100 % larger processing window.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109086"},"PeriodicalIF":1.4,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143430301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ying Ji , Linna Zhao , Shilong Yang , Cunli Lu , Xiaofeng Gu , Wai Tung Ng
{"title":"Degradation mechanisms for static and dynamic characteristics in 1.2 kV 4H-SiC MOSFETs under repetitive short-circuit tests","authors":"Ying Ji , Linna Zhao , Shilong Yang , Cunli Lu , Xiaofeng Gu , Wai Tung Ng","doi":"10.1016/j.sse.2025.109082","DOIUrl":"10.1016/j.sse.2025.109082","url":null,"abstract":"<div><div>In this paper, repetitive short-circuit (RSC) tests are conducted at off-state and on-state gate-source voltages (<em>V</em><sub>GS,OFF</sub>/<em>V</em><sub>GS,ON</sub>) of −4/+15 V, −4/+19 V and 0/+19 V, respectively, to investigate the degradation behaviors of 1.2 kV 4H-SiC MOSFETs. Combining experimental and simulation results, it is found that trapped electrons or holes in the gate oxide during the avalanche process are the main degradation mechanism for the static parameters. This results in increases of 0.4 V and 3.0 mΩ in <em>V</em><sub>TH</sub> and <em>R</em><sub>DS,ON</sub>, respectively, at <em>V</em><sub>GS,OFF</sub>/<em>V</em><sub>GS,ON</sub> = −4/+19 V; 0.45 V and 4.1 mΩ at <em>V</em><sub>GS,OFF</sub>/<em>V</em><sub>GS,ON</sub> = 0/+19 V; and decreases of 0.69 V and 3.2 mΩ at <em>V</em><sub>GS,OFF</sub>/<em>V</em><sub>GS,ON</sub> = −4/+15 V after 240 short-circuit (SC) tests. The dynamic characteristics of the device under test, including <em>C</em><sub>GS</sub>, <em>C</em><sub>DS</sub>, <em>C</em><sub>GD</sub> also degrade. The trapped holes in the gate oxide above the JFET region lead to a thinner depletion region and an obvious increase in <em>C</em><sub>GD</sub>. Furthermore, the gate leakage current under high reverse gate bias is affected by the RSC tests, primarily attributed to trapped electrons hopping to the poly-Si/SiO<sub>2</sub> interface via defect states.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109082"},"PeriodicalIF":1.4,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}