Solid-state Electronics最新文献_第6页

Neural Network-Based prediction for Cross-Temperature induced VT distribution shift in 3D NAND flash memory 基于神经网络的 3D NAND 闪存跨温度诱导 VT 分布偏移预测

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-04-12 DOI: 10.1016/j.sse.2024.108925

Kyeongrae Cho , Chanyang Park , Hyundong Jang , Hyeok Yun , Seungjoon Eom , Min Sang Park , Rock-Hyun Baek

{"title":"Neural Network-Based prediction for Cross-Temperature induced VT distribution shift in 3D NAND flash memory","authors":"Kyeongrae Cho , Chanyang Park , Hyundong Jang , Hyeok Yun , Seungjoon Eom , Min Sang Park , Rock-Hyun Baek","doi":"10.1016/j.sse.2024.108925","DOIUrl":"10.1016/j.sse.2024.108925","url":null,"abstract":"<div>In this study, a neural network (NN) was proposed for predicting the VT characteristics of NAND flash memories under cross-temperature conditions. The training data were obtained from commercial NAND flash memory chip measurements at various temperatures. The VT distribution shift caused by cross-temperature was accurately predicted by investigating the optimum data dimensions while minimizing the data generation process. Two types of NNs were used to achieve an accurate VT distribution prediction, and each network was optimized using specific parameters based on the data characteristics at various program verify levels. Finally, quantitative and visual evaluations were conducted to verify the performance of the trained NNs. When the program-measured temperature varied from low to high, the NNs achieved mean errors of 1.87%, 1.41% at low and 0.34%, 0.77% at high for the average and width of the VT distribution, respectively. Similarly, when the temperature varied from high to low, the corresponding mean errors were 2.01%, 0.74% at high and 0.23%, 1.59% at low. These findings demonstrate that NNs can minimize the procedures for detecting the VT distribution shift caused by cross-temperature, thereby offering a promising approach to enhance reliability in the presence of such effects.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108925"},"PeriodicalIF":1.7,"publicationDate":"2024-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140756730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

BCl3/Cl2 plasma etching process to fabricate a ferroelectric gate structure for device integration 利用 BCl3/Cl2 等离子体蚀刻工艺制造用于器件集成的铁电栅极结构

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-04-06 DOI: 10.1016/j.sse.2024.108918

Bohyeon Kang, Sung-min Ahn, Jongseo Park, Jehyun An, Giryun Hong, Beomjoo Ham, Rock-Hyun Baek

{"title":"BCl3/Cl2 plasma etching process to fabricate a ferroelectric gate structure for device integration","authors":"Bohyeon Kang, Sung-min Ahn, Jongseo Park, Jehyun An, Giryun Hong, Beomjoo Ham, Rock-Hyun Baek","doi":"10.1016/j.sse.2024.108918","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108918","url":null,"abstract":"<div>Despite the significant potential of ferroelectric devices in overcoming the challenges faced by conventional high-k-based CMOS devices owing to the scaling of CMOS processes, most ferroelectric devices are not implemented in practical circuits yet. For practical application, integrating them into a circuit is essential, and the development of a reliable etching process is crucial for the integration of individual devices into circuits. Therefore, this study proposes a process for etching hafnium zirconium oxide (HZO)-based gate stacks to fabricate a gate structure and integrate HZO-based devices into circuits. First, poly-Si/TiN/HZO/TiN/SiO2 was deposited on a Si substrate and etched via Cl2 and BCl3/Cl2 plasma etchings. Cl2 plasma etching was found to be less effective, whereas BCl3/Cl2 plasma etching exhibited a higher etching rate. The optimal etching time for the BCl3/Cl2 plasma at which the entire stack was successfully removed was 50 s. Furthermore, the optimal ratio of Ar:Cl2:BCl3 that resulted in minimal damage to the Si surface was determined to be 1:1:3. These results led to the successful formation of an HZO-based gate structure and provided the potential to integrate ferroelectric devices into the circuit, thereby enabling their practical utilization.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"216 ","pages":"Article 108918"},"PeriodicalIF":1.7,"publicationDate":"2024-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140536834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of breakdown voltage for GaN MIS-HEMT with various composite field plate configurations and passivation layers 采用不同复合场板配置和钝化层的 GaN MIS-HEMT 击穿电压分析

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-04-03 DOI: 10.1016/j.sse.2024.108930

Catherine Langpoklakpam , Yi-Kai Hsiao , Edward Yi Chang , Chun-Hsiung Lin , Hao-Chung Kuo

{"title":"Analysis of breakdown voltage for GaN MIS-HEMT with various composite field plate configurations and passivation layers","authors":"Catherine Langpoklakpam , Yi-Kai Hsiao , Edward Yi Chang , Chun-Hsiung Lin , Hao-Chung Kuo","doi":"10.1016/j.sse.2024.108930","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108930","url":null,"abstract":"<div>The effects of different field plate designs on the breakdown voltage of GaN Metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) were examined in this study. The study's primary goal was to determine the dependence of breakdown voltage with respective to composite field plate designs using TCAD simulation. For devices featuring only G-FP, with a fixed gate to drain distance of 15 μm and a fixed G-FP to drain distance of 15 μm, the maximum breakdown voltage was achieved 1 μm G-FP. Breakdown voltage trends were also determined for composite field plate configurations, such as adding a source field plate (S-FP) or a drain field plate (D-FP) with a fixed 1 μm G-FP length. A further enhancement in device breakdown performance was demonstrated by employing a novel D-FP structure. A single D-FP improves the breakdown voltage from 1.4 kV (conventional breakdown voltage with 1um G-FP) to 1.6 kV when combined with 1 μm G-FP, while the novel two-step D-FP achieves a breakdown voltage of about 1.7 kV when combined with 1 μm G-FP. We also investigated the influence of high-k dielectric passivation layers on the breakdown voltage. The breakdown voltage of the devices with optimized G-FP can be further improved by using high-k dielectric material as a passivation layer. The thorough investigations contribute to a better understanding of GaN MIS-HEMT breakdown characteristics and prospective pathways for improving their performance via unique field plate designs and superior dielectric materials.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"216 ","pages":"Article 108930"},"PeriodicalIF":1.7,"publicationDate":"2024-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140557630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improvement of instrumentation consistency using DUV filter in Spectroscopic Ellipsometry 在光谱椭偏仪中使用 DUV 滤波器提高仪器一致性

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-04-03 DOI: 10.1016/j.sse.2024.108912

Yu-Seong Gim, Yong-Woo Jung, Jong-Seok Yi, Kang-Won Lee

引用次数: 0

Proposed package type for evaluating reliability of HBM Memory 用于评估 HBM 内存可靠性的拟议封装类型

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-04-03 DOI: 10.1016/j.sse.2024.108923

Dongsoo Lee, G.H. Bae, J.S. Bae, N.H. Lee, Y.S. Lee, S.B. Ko

引用次数: 0

A wireless neural recording microsystem with operator-based spike detection 具有基于操作员的尖峰检测功能的无线神经记录微型系统

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-04-03 DOI: 10.1016/j.sse.2024.108915

Joonyoung Lim , Chae-Eun Lee , Jong-Hyun Park , Chieun Choi , Yoon-Kyu Song

引用次数: 0

A wireless stimulator system-on-chip with an optically writable ID for addressable cortical microimplants 用于可寻址皮层微植入物的带有光学可写 ID 的无线刺激器片上系统

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-04-03 DOI: 10.1016/j.sse.2024.108914

Chae-Eun Lee , Jong-Hyun Park , Joonyoung Lim , Chieun Choi , Yoon-Kyu Song

{"title":"A wireless stimulator system-on-chip with an optically writable ID for addressable cortical microimplants","authors":"Chae-Eun Lee , Jong-Hyun Park , Joonyoung Lim , Chieun Choi , Yoon-Kyu Song","doi":"10.1016/j.sse.2024.108914","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108914","url":null,"abstract":"<div>For a profound understanding of brain function and connectivity, there is an escalating need to cover expansive cortical areas. While external recording methods such as electroencephalography (EEG) are prevalent, direct bidirectional interaction with the neural network mandates implanted electrodes. Integrating all microimplant functionalities into a single integrated circuit (IC) increases design complexities. Thus, challenges in the intricacies of distributed system networking have frustrated the drive toward implant miniaturization. In this context, we introduce addressable microimplants equipped with gate oxide-based anti-fuse (AF) Chip-IDs activated by a photodiode (PD) array. This mechanism generates a binary ID code by selectively degrading the anti-fuse gate oxide, eliminating the need for I/O PADs. These ID-equipped wireless micro-implants are distributed over vast regions, enabling bidirectional neural interfacing through recording and stimulation. We successfully fabricated an 8-channel wireless microstimulator and a spike-sensor in 180 nm CMOS, demonstrating the efficacy of the 5-bit Chip-ID in real-time networking scenarios. The system draws power from RF electromagnetic waves, receiving 1.2 V and 1 mW, and employs amplitude modulation at a 900 MHz carrier frequency for data communication. The minimum amplitude detected for demodulation was 350 mV, regenerating a 1 MHz clock and 34-bit command data. When tested, the array of eight microstimulators responded distinctly based on sequential command parameters. This IC realized in TSMC 180 nm CMOS technology, occupies only a 1 mm2 area.</div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"216 ","pages":"Article 108914"},"PeriodicalIF":1.7,"publicationDate":"2024-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140347842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of electrical and hysteresis characteristics of flexible OTFT using solution-processable DPP-DTT polymer and Parylene-C 使用可溶液加工的 DPP-DTT 聚合物和对二甲苯-C 分析柔性 OTFT 的电气和磁滞特性

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-03-31 DOI: 10.1016/j.sse.2024.108922

Yoojeong Ko, Hyo-Won Jang, Hyeok Kim, Dong-Wook Park

引用次数: 0

Analysis of metal and zinc oxide semiconductor interface resistance using transmission line method 利用传输线方法分析金属和氧化锌半导体界面电阻

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-03-30 DOI: 10.1016/j.sse.2024.108916

Do-Yeon Lee, Woon-San Ko, Ki-Nam Kim, Jun-Ho Byun, Eun-Gi Kim, So-Yeon Kwon, Ga-Won Lee

引用次数: 0

Multi-level storage in cleaved-gate ferroelectric FETs investigated by 3D phase-field-based quantum transport simulation 通过基于三维相场的量子输运模拟研究裂隙栅铁电场效应晶体管中的多级存储

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-03-30 DOI: 10.1016/j.sse.2024.108928

Jeonghwan Jang, Hyeongu Lee, Mincheol Shin

引用次数: 0