Comparison of impact of channel length- and width-directional taper angle in nanosheet and forksheet FETs for 2 nm node and beyond

Abstract

Herein, an analysis of nanosheet field-effect transistors (NSFETs) and forksheet field-effect transistors (FSFETs) with 3 and 4 channel stacks is performed using fully calibrated technology computer-aided design (TCAD), to study the effect of the taper angle. Variations in the channel length- (A_NS,L) and width-directional (A_NS,W) angles, which inevitably occur during anisotropic etching, significantly affect both DC and AC performance. As A_NS,L decreases, the longer channel decreases subthreshold swing (SS) and increases ballistic mobility, thereby improving the on-state current (I_on). However, at smaller A_NS,L values, the source/drain (S/D) epitaxial volume decreases, reducing the stress on the channel and consequently decreasing I_on. Additionally, the on-state gate capacitance (C_{gg_on}) increases as A_NS,L decreases. In contrast, a smaller A_NS,W increases I_on due to the increased effective channel width (W_eff). Notably, the 4-stack configuration shows a larger I_on than the 3-stack as A_NS,W decreases, attributed to the additional W_eff in the bottom channel of the 4-stack. Similar to A_NS,L, C_{gg_on} increases as A_NS,W decreases. As all-directional taper angle (A_NS,B) decreases, both I_on and C_{gg_on} increase because A_NS,L and A_NS,W simultaneously influence these parameters. Although this effect increases the RC delay in both NSFETs and FSFETs as A_NS,B decreases, FSFETs are more sensitive to RC delay than NSFETs. Furthermore, 4-stack FSFETs exhibit significant degradation in RC delay compared to NSFETs, owing to their high RC delay sensitivity in high-stack configurations. Despite the advantages of FSFETs over NSFETs in terms of RC delay and area reduction, these results indicate that FSFETs are highly sensitive to taper angle variations, particularly in high-stack configurations, potentially negating their RC delay benefits.