迈向用于pet器件制造的sSOI衬底的完全松弛

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-07-25 DOI:10.1016/j.sse.2025.109196

N-P. Tran, F. Milesi, V-H. Le, L-D. Mohgouk Zouknak, P. Dezest, Ph. Rodriguez, L. Brunet, B. Duriez, M-C. Cyrille, C. Fenouillet-Beranger

{"title":"迈向用于pet器件制造的sSOI衬底的完全松弛","authors":"N-P. Tran, F. Milesi, V-H. Le, L-D. Mohgouk Zouknak, P. Dezest, Ph. Rodriguez, L. Brunet, B. Duriez, M-C. Cyrille, C. Fenouillet-Beranger","doi":"10.1016/j.sse.2025.109196","DOIUrl":null,"url":null,"abstract":"<div><div>The new generation of 10 nm FDSOI requires more performance enhancers to increase mobility in the channels, where electron mobility is improved by tensile stress for nMOS and hole mobility is improved by compressive stress for pMOS. Therefore, strained silicon-on-insulator (sSOI) wafers are considered to improve nMOS performance. In the case of using sSOI wafers, relaxing the tensile silicon for PMOS appears to be beneficial to facilitate the Ge condensation process. In this paper, we demonstrate over 90 % relaxation from a 1.25 GPa tensile sSOI starting wafer. Multiple iterations of ion implantation and annealing are also investigated and may provide a path for further relaxation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109196"},"PeriodicalIF":1.4000,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Toward full relaxation of sSOI substrates for PFET device fabrication\",\"authors\":\"N-P. Tran, F. Milesi, V-H. Le, L-D. Mohgouk Zouknak, P. Dezest, Ph. Rodriguez, L. Brunet, B. Duriez, M-C. Cyrille, C. Fenouillet-Beranger\",\"doi\":\"10.1016/j.sse.2025.109196\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>The new generation of 10 nm FDSOI requires more performance enhancers to increase mobility in the channels, where electron mobility is improved by tensile stress for nMOS and hole mobility is improved by compressive stress for pMOS. Therefore, strained silicon-on-insulator (sSOI) wafers are considered to improve nMOS performance. In the case of using sSOI wafers, relaxing the tensile silicon for PMOS appears to be beneficial to facilitate the Ge condensation process. In this paper, we demonstrate over 90 % relaxation from a 1.25 GPa tensile sSOI starting wafer. Multiple iterations of ion implantation and annealing are also investigated and may provide a path for further relaxation.</div></div>\",\"PeriodicalId\":21909,\"journal\":{\"name\":\"Solid-state Electronics\",\"volume\":\"229 \",\"pages\":\"Article 109196\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-07-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid-state Electronics\",\"FirstCategoryId\":\"101\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0038110125001418\",\"RegionNum\":4,\"RegionCategory\":\"物理与天体物理\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125001418","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

新一代10纳米FDSOI需要更多的性能增强剂来提高通道中的迁移率，其中nMOS的拉伸应力提高了电子迁移率，pMOS的压缩应力提高了空穴迁移率。因此，应变绝缘体上硅（sSOI）晶圆被认为可以改善nMOS的性能。在使用sSOI晶圆的情况下，放松PMOS的拉伸硅似乎有利于促进Ge凝聚过程。在本文中，我们证明了在1.25 GPa的拉伸sSOI晶圆上有超过90%的弛豫。离子注入和退火的多次迭代也被研究，并可能提供进一步弛豫的途径。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Toward full relaxation of sSOI substrates for PFET device fabrication

The new generation of 10 nm FDSOI requires more performance enhancers to increase mobility in the channels, where electron mobility is improved by tensile stress for nMOS and hole mobility is improved by compressive stress for pMOS. Therefore, strained silicon-on-insulator (sSOI) wafers are considered to improve nMOS performance. In the case of using sSOI wafers, relaxing the tensile silicon for PMOS appears to be beneficial to facilitate the Ge condensation process. In this paper, we demonstrate over 90 % relaxation from a 1.25 GPa tensile sSOI starting wafer. Multiple iterations of ion implantation and annealing are also investigated and may provide a path for further relaxation.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.