Solid-state Electronics最新文献_第7页

A multi-stage neural network I-V and C-V BSIM-CMG model global parameter extractor for advanced GAAFET technologies 用于先进GAAFET技术的多级神经网络I-V和C-V BSIM-CMG模型全局参数提取器

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-11 DOI: 10.1016/j.sse.2025.109081

Jen-Hao Chen , Fredo Chavez , Chien-Ting Tung , Sourabh Khandelwal , Chenming Hu

{"title":"A multi-stage neural network I-V and C-V BSIM-CMG model global parameter extractor for advanced GAAFET technologies","authors":"Jen-Hao Chen , Fredo Chavez , Chien-Ting Tung , Sourabh Khandelwal , Chenming Hu","doi":"10.1016/j.sse.2025.109081","DOIUrl":"10.1016/j.sse.2025.109081","url":null,"abstract":"<div><div>A I-V and C-V parameter extraction methodology with various gate lengths utilizing a multi-stage neural network is proposed. This multi-stage neural network contains four networks focusing on extracting parameters from four different regions in transistor’s characteristics, enabling a machine to emulate human’s parameter extraction strategy. This methodology begins with the generation of a training dataset through Monte Carlo simulation, varying 53 selected IV and CV BSIM-CMG model parameters. With each Monte Carlo-selected parameter set, the I-V, transconductance, output conductance and C-V characteristics of seven different GAAFETs with different gate lengths ranging from 9 nm to 389 nm are generated. This multi-stage neural network is trained with the GAAFETs’ characteristics as the input and the 53 model parameters as the output. After training, TCAD-generated GAAFET I-V, conductance and C-V data with various gate lengths are used to test this neural network parameter extractor’s ability of extracting BSIM-CMG model parameters that generate data accurately fitting the TCAD IV and CV data. It is demonstrated that this parameter extraction neural network can extract BSIM-CMG model parameters’ value for GAAFETs within few seconds.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109081"},"PeriodicalIF":1.4,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Some considerations about Lambert W function-based nanoscale MOSFET charge control modeling 基于Lambert W函数的纳米MOSFET电荷控制建模的一些思考

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-04 DOI: 10.1016/j.sse.2025.109080

A. Ortiz-Conde , V.C.P. Silva , P.G.D. Agopian , J.A. Martino , F.J. García-Sánchez

{"title":"Some considerations about Lambert W function-based nanoscale MOSFET charge control modeling","authors":"A. Ortiz-Conde , V.C.P. Silva , P.G.D. Agopian , J.A. Martino , F.J. García-Sánchez","doi":"10.1016/j.sse.2025.109080","DOIUrl":"10.1016/j.sse.2025.109080","url":null,"abstract":"<div><div>The unwanted low-level doping present in supposedly undoped MOSFET channels has a significant effect on charge control and Lambert W function-based inversion charge MOSFET models, as well as on subsequent drain current models. We show that the hypothetical intrinsic MOSFET channel approximation, often used to describe a nominally undoped channel, produces significant errors, even for the low-level concentrations resulting from unintentional doping. We show that the traditional charge control model, which mathematically describes the gate voltage as the sum of one linear and one logarithmic term of the inversion charge, is only valid for the hypothetically intrinsic case. However, it may still be used for nominally undoped but unintentionally low-doped channel devices within the region of operation where the majority carriers are the dominant charge. With this in mind, we present here a better approximation of the nominally undoped MOSFET channel surface potential. We also propose an improved modified expression that describes the gate voltage as the sum of one linear and two logarithmic terms of the inversion charge. A new approximate drain current control formulation is also proposed to account for parasitic series resistance and/or mobility degradation. The new model agrees reasonably well with measurement data from nominally undoped vertically stacked GAA Si Nano Sheet MOSFETs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109080"},"PeriodicalIF":1.4,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143377726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of the mobility behavior of MOS2 2D FETs MOS2二维场效应管的迁移行为分析

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-01 DOI: 10.1016/j.sse.2024.109032

Antonio Cerdeira , Magali Estrada , Ahmed Mounir , Tibor Grasser , Benjamín Iñiguez

引用次数: 0

Comprehensive analysis of MOSFET threshold voltage extraction method considering DIBL effect from 300 K down to 10 K 综合分析考虑DIBL效应的MOSFET阈值电压提取方法，从300 K降至10 K

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-01 DOI: 10.1016/j.sse.2024.109045

Zhizhao Ma , Hao Su , Yuhuan Lin , Shenghua Zhou , Feichi Zhou , Xiaoguang Liu , Longyang Lin , Yida Li , Kai Chen

{"title":"Comprehensive analysis of MOSFET threshold voltage extraction method considering DIBL effect from 300 K down to 10 K","authors":"Zhizhao Ma , Hao Su , Yuhuan Lin , Shenghua Zhou , Feichi Zhou , Xiaoguang Liu , Longyang Lin , Yida Li , Kai Chen","doi":"10.1016/j.sse.2024.109045","DOIUrl":"10.1016/j.sse.2024.109045","url":null,"abstract":"<div><div>It is well known that different threshold voltage <em>(V<sub>th</sub>)</em> extraction methods exhibit inconsistencies with respect to different drain voltage (<em>V<sub>d</sub></em>). This inconsistency becomes disruptive when temperature is considered for cryogenic applications such as quantum computing. This investigation examines various <em>V<sub>th</sub></em> extraction methods from room down to cryogenic temperatures, with a particular emphasis on how different <em>V<sub>d</sub></em> values combined with extraction methods behave as temperature decreases. For the first time, we find that the square root <em>I<sub>d</sub></em> method maintains consistency regardless of <em>V<sub>d</sub></em>, from 300 K all the way down to 10 K is identified. This provides a good insight into how the Drain-Induced Barrier Lowering (DIBL) effect changes with temperature, and positions the square root <em>I<sub>d</sub></em> method as a reliable tool for <em>V<sub>th</sub></em> extraction in cryogenic temperature.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109045"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Suppression of de-trapping by remanent polarization in dual-mechanism flash memory 双机制快闪记忆体中残余极化抑制去阱

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-01 DOI: 10.1016/j.sse.2024.109049

Eui Joong Shin, Jaejoong Jeong, Gyusoup Lee, Seongho Kim, Byung Jin Cho

引用次数: 0

Simulation and experimental Demonstration on A retrograde drift LDMOS 一种逆行漂移LDMOS的仿真与实验论证

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-01 DOI: 10.1016/j.sse.2024.109050

Shaoxin Yu , Rongsheng Chen , Weiheng Shao , Xiaoyan Zhao , Zheng Chen , Weizhong Shan , Jenhao Cheng

{"title":"Simulation and experimental Demonstration on A retrograde drift LDMOS","authors":"Shaoxin Yu , Rongsheng Chen , Weiheng Shao , Xiaoyan Zhao , Zheng Chen , Weizhong Shan , Jenhao Cheng","doi":"10.1016/j.sse.2024.109050","DOIUrl":"10.1016/j.sse.2024.109050","url":null,"abstract":"<div><div>In this article, an RD (Retrograde drift) LDMOS (Lateral double diffused metal oxide semiconductor) device is introduced. The drift region in this proposed device is trapezoidal in shape and gradually decreases from top to bottom in doping concentration, called “retrograde drift.” Simulations indicate that this RD device has an 11.7% lower electric field peak value, 6.2% lower potential under the poly gate, 32.1% higher current width in the drift region, and 10.5% lower impact gen rate at the corner of FP (Field plate) as well. A series of devices have been fabricated using a photoresist treatment process. Compared with the conventional BD (box-shape drift) device, the RD device’s <span><math><mrow><mi>BV</mi></mrow></math></span>(Breakdown voltage)-<span><math><msub><mi>R</mi><mrow><mi>on</mi><mo>,</mo><mi>s</mi><mi>p</mi></mrow></msub></math></span> (on-resistance) FOM (Figure of merit) performance is improved by 30.9%, and the <span><math><msub><mi>Q</mi><mrow><mi>gd</mi></mrow></msub></math></span>(Gate-drain charge)-<span><math><msub><mi>R</mi><mrow><mi>on</mi><mo>,</mo><mi>s</mi><mi>p</mi></mrow></msub></math></span> FOM character is improved by 42.1%. Moreover, the RD device owns better HCI (Hot carrier injection) performance on both <span><math><msub><mi>R</mi><mrow><mi>on</mi><mo>,</mo><mi>s</mi><mi>p</mi></mrow></msub></math></span> degradation and <span><math><msub><mi>V</mi><mi>T</mi></msub></math></span> (Threshold voltage) degradation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109050"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Editorial. Special issue. EUROSOI-ULIS 2023 社论。特殊的问题。EUROSOI-ULIS 2023

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-01 DOI: 10.1016/j.sse.2024.109030

Benjamin Iniguez, Francisco Gamiz

引用次数: 0

Equivalence of proton-induced displacement damage in InP-based HEMT 基于inp的HEMT中质子诱导位移损伤的等效性

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-01 DOI: 10.1016/j.sse.2024.109048

Bo Liu , Yong-Bo Su , Ren-Jie Liu , Zhi Jin , Chao Zhang , Ying-Hui Zhong

引用次数: 0

GatedNN: An accurate deep learning-based parameter extraction for BSIM-CMG 基于深度学习的BSIM-CMG精确参数提取方法

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-01 DOI: 10.1016/j.sse.2024.109044

Guangxin Guo, Zhengguang Tang, Zhenhai Cui, Cong Li, Hailong You

{"title":"GatedNN: An accurate deep learning-based parameter extraction for BSIM-CMG","authors":"Guangxin Guo, Zhengguang Tang, Zhenhai Cui, Cong Li, Hailong You","doi":"10.1016/j.sse.2024.109044","DOIUrl":"10.1016/j.sse.2024.109044","url":null,"abstract":"<div><div>An enhanced deep learning (DL) -based parameter extraction method for transistor compact models, named GatedNN, is introduced. GatedNN achieves significant accuracy improvements over existing DL-based parameter extraction techniques. The innovation lies in incorporating neural network (NN) with gating mechanism and compact model-aware techniques: model parameter importance analysis and model quality check. The GatedNN uses gates to resolve optimization conflicts among model parameters by controlling gradient descent during training. The importance analysis focuses on optimizing more crucial parameters that contribute to the current curve. The model quality check cleans the training data fed to the GatedNN and ensures the robustness of the NN output. Evaluated on the BSIM-CMG model with measured FinFET data, the proposed approach demonstrates a substantial 69% error reduction compared to recently DL-based parameter extractor. Furthermore, the scalability and mathematical robustness of the generated model are tested. The proposed GatedNN also provides insights into model parameters and device characteristics, aiding in understanding and adjusting for desired characteristics. We believe the developed method can advance the development of DL-based parameter extraction.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"224 ","pages":"Article 109044"},"PeriodicalIF":1.4,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143147214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced threshold voltage tuning in FD-SOI MOSFET with ferroelectric buried oxide 铁电埋藏氧化物增强FD-SOI MOSFET的阈值电压调谐

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-02-01 DOI: 10.1016/j.sse.2024.109052

Sorin Cristoloveanu , Etienne Nowak , Justine Barbot , Laurent Grenouillet , Ionut Radu

引用次数: 0