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Analytical modeling of nanoscale double-gate junctionless transistors comprising the impact of the source and drain underlap regions 纳米级双栅无结晶体管的解析建模,包括源极和漏极下搭区影响
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-03-25 DOI: 10.1016/j.sse.2025.109105
Miltiadis K. Nakos , Andreas Tsormpatzoglou , Dimitrios H. Tassis , Theodoros A. Oproglidis , Constantinos T. Angelis , Charalabos A. Dimitriadis
{"title":"Analytical modeling of nanoscale double-gate junctionless transistors comprising the impact of the source and drain underlap regions","authors":"Miltiadis K. Nakos ,&nbsp;Andreas Tsormpatzoglou ,&nbsp;Dimitrios H. Tassis ,&nbsp;Theodoros A. Oproglidis ,&nbsp;Constantinos T. Angelis ,&nbsp;Charalabos A. Dimitriadis","doi":"10.1016/j.sse.2025.109105","DOIUrl":"10.1016/j.sse.2025.109105","url":null,"abstract":"<div><div>In this study, we investigate the impact of the source and drain (S/D) underlap regions on the electrical characteristics of short-channel double-gate junctionless transistors (DG JLTs). Analytical expression for the potential distribution in the gate overlap and S/D underlap regions is introduced, which relies on a single fitting parameter and the gate fringe capacitance in the underlap regions. The derived potential distribution shows good agreement with simulation results across different underlap lengths and gate/drain bias voltages. Consequently, new expressions for the threshold voltage and the subthreshold swing coefficient of DG JLTs are developed comprising the effect of the S/D underlap regions, which are used for upgrading our previous continuous and symmetric analytical drain current compact model. The findings highlight the significant influence of the S/D underlap regions on the electrical characteristics of DG JLTs, suggesting a need for their careful consideration in drain current compact modeling.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109105"},"PeriodicalIF":1.4,"publicationDate":"2025-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143725758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Recent progress in bipolar and heterojunction bipolar transistors on SOI SOI上双极和异质结双极晶体管的研究进展
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-03-20 DOI: 10.1016/j.sse.2025.109101
Soumya Ranjan Panda , Thomas Zimmer , Anjan Chakravorty , Sebastien Fregonese
{"title":"Recent progress in bipolar and heterojunction bipolar transistors on SOI","authors":"Soumya Ranjan Panda ,&nbsp;Thomas Zimmer ,&nbsp;Anjan Chakravorty ,&nbsp;Sebastien Fregonese","doi":"10.1016/j.sse.2025.109101","DOIUrl":"10.1016/j.sse.2025.109101","url":null,"abstract":"<div><div>This article discusses the intricate advancements in lateral bipolar transistors (LBJT) and devices based on silicon germanium (SiGe) lateral hetero-junction bipolar transistors (LHBT). The paper also addresses the developments in vertical SiGe HBTs, and the challenges encountered in fabricating vertical devices on SOI substrates and demonstrates how these hurdles can be mitigated through lateral device technology. Owing to their compatibility with the complementary metal–oxide–semiconductor (CMOS) field effect transistor (FET) process and their appealing prospects in mixed-signal radio frequency applications, SiGe HBT devices remain a compelling choice. Integrating silicon-on-insulator (SOI) substrates eliminates parasitic components, rendering it to be an attractive option when coupled with SiGe HBT technology. This article explores various SOI-based lateral devices, elucidating their architectures and performance characteristics. It notably underscores our recent endeavors concerning the 28 nm fully-depleted SOI (FDSOI)-based SiGe HBT.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109101"},"PeriodicalIF":1.4,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143696924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Expanding the potential of Zn0.15Sn0.85(Se0.95S0.05)2 crystals for applications in near-infrared optoelectronics, sensing, and Van der Waals heterojunctions 扩大Zn0.15Sn0.85(Se0.95S0.05)2晶体在近红外光电子学、传感和范德华异质结中的应用潜力
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-03-15 DOI: 10.1016/j.sse.2025.109104
Yash N. Doshi , Dixita S. Parmar , Ajay D. Zanpadiya , Aditi P. Pathak , Divya R. Solanki , Dimple V. Shah , Vishva M. Jain , Hiren N. Desai , Piyush B. Patel
{"title":"Expanding the potential of Zn0.15Sn0.85(Se0.95S0.05)2 crystals for applications in near-infrared optoelectronics, sensing, and Van der Waals heterojunctions","authors":"Yash N. Doshi ,&nbsp;Dixita S. Parmar ,&nbsp;Ajay D. Zanpadiya ,&nbsp;Aditi P. Pathak ,&nbsp;Divya R. Solanki ,&nbsp;Dimple V. Shah ,&nbsp;Vishva M. Jain ,&nbsp;Hiren N. Desai ,&nbsp;Piyush B. Patel","doi":"10.1016/j.sse.2025.109104","DOIUrl":"10.1016/j.sse.2025.109104","url":null,"abstract":"<div><div>Layered Zn<sub>0.15</sub>Sn<sub>0.85</sub>(Se<sub>0.95</sub>S<sub>0.05</sub>)<sub>2</sub> (Q2) crystals with a hexagonal crystalline structure were grown using the direct vapor transport technique (DVT). This research explores applications of the grown Q2 crystals as a near-infrared (NIR) photodetector, vacuum pressure sensor, and Van der Waals heterojunction. The NIR photodetector demonstrating stable, rapid switching with an improved responsivity of 153.38 mAW<sup>-1</sup>. A Q2 crystal-based NIR photodetector achieves an external quantum efficiency of 21.17 %. The Maxwellian distribution was applied to analysis trap depth of NIR photodetector. Additionally, the pulse resistive response of the Q2 crystal-based vacuum pressure sensor was evaluated across a vacuum pressure range from −1033 mbar to 0 mbar. The sensor exhibited a stable response, with 61.27 % at −1033 mbar and 5.85 % at −133 mbar with an average delay time of 2.99 s. Furthermore, the Van der Waals heterojunction device formed by the grown p-type Q2 crystals with another n-type quaternary crystal was studied using the thermionic-emission (TE) model. The ideality factors have been defined in the range of 1 to 2 by studying the current voltage (I-V) characteristics under different temperatures.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109104"},"PeriodicalIF":1.4,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143642555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Intense near-infrared electroluminescence properties from ZnO:Yb LED ZnO:Yb LED的强近红外电致发光特性
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-03-12 DOI: 10.1016/j.sse.2025.109102
Qingxue Zhao , Shenwei Wang , Zhengmao Wen , Weifang Zhang , Xiaoxia Duan , Lixin Yi
{"title":"Intense near-infrared electroluminescence properties from ZnO:Yb LED","authors":"Qingxue Zhao ,&nbsp;Shenwei Wang ,&nbsp;Zhengmao Wen ,&nbsp;Weifang Zhang ,&nbsp;Xiaoxia Duan ,&nbsp;Lixin Yi","doi":"10.1016/j.sse.2025.109102","DOIUrl":"10.1016/j.sse.2025.109102","url":null,"abstract":"<div><div>Rare-earth (RE) doped zinc oxide electroluminescence is worthy of study due to its pure and sharp luminescence characteristics. In this work, we report ZnO:Yb light-emitting diodes (LED) and test their electroluminescence properties. Through adjusting the concentration of ytterbium doping and optimizing of annealing parameters for ZnO:Yb thin films, the results show that ZnO:Yb light-emitting diodes are capable of generating intense near-infrared emission at 975 nm and 1004 nm. We contend that impact excitation is the predominant mechanism underlying the electroluminescence in ITO/PEDOT:PSS/ZnO:Yb/n-Si light-emitting diodes. These results are considered an effective strategy for rare-earth-doped semiconductor electroluminescence in near-infrared light-emitting diodes.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109102"},"PeriodicalIF":1.4,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143628006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Traps characterization in RF SOI substrates including a buried SiGe layer 射频 SOI 基底(包括埋入的 SiGe 层)中的陷波表征
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-03-11 DOI: 10.1016/j.sse.2025.109103
Y. Yan , M. Rack , M. Vanbrabant , M. Nabet , A. Goebel , P. Clifton , J.-P. Raskin
{"title":"Traps characterization in RF SOI substrates including a buried SiGe layer","authors":"Y. Yan ,&nbsp;M. Rack ,&nbsp;M. Vanbrabant ,&nbsp;M. Nabet ,&nbsp;A. Goebel ,&nbsp;P. Clifton ,&nbsp;J.-P. Raskin","doi":"10.1016/j.sse.2025.109103","DOIUrl":"10.1016/j.sse.2025.109103","url":null,"abstract":"<div><div>This work analyzes the interface traps density (<em>D</em><sub>it</sub>) at the SiO<sub>2</sub>/SiGe interface of a buried SiGe stressor SOI substrate, and demonstrates the impact of those traps on the effective resistivity (<em>ρ</em><sub>eff</sub>) of the substrate. The <em>C-V</em> behavior of MOS capacitors and the RF insertion loss along coplanar waveguide transmission lines on various substrates are measured. TCAD simulations are employed to interpret the traps characteristics and to forecast the RF performance of a buried SiGe stressor SOI wafer having a high resistivity handle Si substrate. The results demonstrate that thanks to the interface traps introduced by the SiGe layer the substrate effective resistivity (<em>ρ</em><sub>eff</sub>) is enhanced.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109103"},"PeriodicalIF":1.4,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An efficient temperature dependent compact model for nanosheet FET for neuromorphic computing circuit 用于神经形态计算电路的纳米片场效应晶体管的高效温度相关紧凑模型
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-03-10 DOI: 10.1016/j.sse.2025.109096
N. Aruna Kumari , Abhishek Kumar Upadhyay , Vikas Vijayvargiya , Gaurav Singh , Ankur Beohar , Prithvi P.
{"title":"An efficient temperature dependent compact model for nanosheet FET for neuromorphic computing circuit","authors":"N. Aruna Kumari ,&nbsp;Abhishek Kumar Upadhyay ,&nbsp;Vikas Vijayvargiya ,&nbsp;Gaurav Singh ,&nbsp;Ankur Beohar ,&nbsp;Prithvi P.","doi":"10.1016/j.sse.2025.109096","DOIUrl":"10.1016/j.sse.2025.109096","url":null,"abstract":"<div><div>In this work, a temperature-dependent compact model is proposed for the three-sheet (3S) Nanosheet (NS) FET. This model is developed because a computationally efficient model is needed for large-scale circuit design. The model is based on the virtual source (VS) principle, which is chosen because for its simple mathematical formulation and minimal parameter requirements. This allows the model to accurately capture the performance characteristics of the 3S NSFET. The model is validated using TCAD results, which are well-calibrated with experimental data. It is then implemented in Verilog-A code for neuromorphic circuit simulations. Herein, we analyses the important parameters such as power, energy, and spiking frequency in NSFET-based leaky integrate-and-fire (LIF) neurons, with temperature variations. The results show that as the temperature increased from 25 °C to 125 °C, the spiking frequency increased by 36.64 %, due to higher current in the subthreshold operation of the device.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109096"},"PeriodicalIF":1.4,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143855774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low power consumption of non-volatile memory device by tunneling process engineering 隧道工艺设计的低功耗非易失性存储器
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-03-09 DOI: 10.1016/j.sse.2025.109100
Fucheng Wang , Mengmeng Chu , Jingwen Chen , Zhong Pan , Yongsang Kim , Jang kun Song , Muhammad Quddamah Khokhar , Junsin Yi
{"title":"Low power consumption of non-volatile memory device by tunneling process engineering","authors":"Fucheng Wang ,&nbsp;Mengmeng Chu ,&nbsp;Jingwen Chen ,&nbsp;Zhong Pan ,&nbsp;Yongsang Kim ,&nbsp;Jang kun Song ,&nbsp;Muhammad Quddamah Khokhar ,&nbsp;Junsin Yi","doi":"10.1016/j.sse.2025.109100","DOIUrl":"10.1016/j.sse.2025.109100","url":null,"abstract":"<div><div>Compared with Si<sub>3</sub>N<sub>4</sub> and Al<sub>2</sub>O<sub>3</sub>, SiO<sub>2</sub> grown using thermal oxidation process as tunneling layer has the advantages of high bandgap and well interface contact with the surface of silicon wafer, which can be a great solution to the leakage current problem of metal–insulator-semiconductor (MIS) devices. This study investigates the effect of improving the SiO<sub>2</sub> tunnel layer on the operating voltage of MIS devices with a SiO<sub>2</sub>/HfAlO<sub>x</sub>/Al<sub>2</sub>O<sub>3</sub> structure. The result shows the operating voltage changes as the tunneling layer thickness decreases, with a minimum of only 12 V for a 1.5 nm tunneling layer thickness. In addition, we found that pinholes are generated on the film surface when annealing a 1.5 nm SiO<sub>2</sub> tunnel layer at 850 °C N<sub>2</sub>, in which case the operating voltage of the device is reduced to only 10 V, though it was also accompanied by the deterioration of the retention characteristics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109100"},"PeriodicalIF":1.4,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143627960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Selective grain size enlargement in Contact/Via plugs using Nanosecond green laser annealing 利用纳秒绿色激光退火技术有选择地增大接触/Via 塞的晶粒尺寸
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-03-07 DOI: 10.1016/j.sse.2025.109098
Jaejoong Jeong , Youngkeun Park , Hwanuk Guim , Yongku Baek , Heetae Kim , Dongbin Kim , Hui Jae Cho , Su-hyeon Gwon , Min Ju Kim , Byung Jin Cho
{"title":"Selective grain size enlargement in Contact/Via plugs using Nanosecond green laser annealing","authors":"Jaejoong Jeong ,&nbsp;Youngkeun Park ,&nbsp;Hwanuk Guim ,&nbsp;Yongku Baek ,&nbsp;Heetae Kim ,&nbsp;Dongbin Kim ,&nbsp;Hui Jae Cho ,&nbsp;Su-hyeon Gwon ,&nbsp;Min Ju Kim ,&nbsp;Byung Jin Cho","doi":"10.1016/j.sse.2025.109098","DOIUrl":"10.1016/j.sse.2025.109098","url":null,"abstract":"<div><div>The rapid decrease in interconnect Critical Dimensions (CDs) within logic devices and growth in the contact height of 3D memory devices have led to increased contact/via plugs resistance. In this study, we introduce an approach to reduce the resistance of the contact/via plugs by engineering the grain size of the plugs using Nanosecond Green Laser Annealing (NGLA) with a low energy fluence (= 0.1 J/cm<sup>2</sup>). Because of the proximity between adjacent W plugs, diffraction of the laser light can occur which will help the laser energy to be absorbed by the sidewall of the W plugs. In addition, the difference in reflectivity between the plug region and W interconnect lines can cause grain size enlargement to selectively occur in the plug region. The NGLA process increased grain size in the plugs up to 79.9 %, resulting as much as a 26 % reduction in tungsten plug resistance. The standard deviation of the plug resistance was also improved from 14.6 % to 7.9 % after the NGLA process.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109098"},"PeriodicalIF":1.4,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-frequency noise in polysilicon Source-Gated Thin-Film transistors 多晶硅源门控薄膜晶体管中的低频噪声
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-03-03 DOI: 10.1016/j.sse.2025.109099
Q. Chen , L.Van Brandt , V. Kilchytska , E. Bestelink , R.A. Sporea , D. Flandre
{"title":"Low-frequency noise in polysilicon Source-Gated Thin-Film transistors","authors":"Q. Chen ,&nbsp;L.Van Brandt ,&nbsp;V. Kilchytska ,&nbsp;E. Bestelink ,&nbsp;R.A. Sporea ,&nbsp;D. Flandre","doi":"10.1016/j.sse.2025.109099","DOIUrl":"10.1016/j.sse.2025.109099","url":null,"abstract":"<div><div>The low-frequency noise (LFN) of thin-film polysilicon source-gated transistors (SGTs) is investigated. DC characteristics were firstly measured and typical behaviors of SGT were observed. Then, TCAD simulations were performed with different doping concentrations. Current density distribution shows that the variation of the conduction channel position in the thin film induces a second plateau in the (<em>g</em><sub>m</sub>/<em>I</em><sub>D</sub>)<sup>2</sup> curves for bias points in subthreshold region. LFN was measured for both SGTs and thin-film field-effect transistor (TFTs) configurations. 1/<em>f</em> noise is confirmed as the main component of LFN in all our measurements. Carrier mobility fluctuation (CMF) is found to dominate the origin of LFN in TFT configuration and the low-current region of SGT. In the high-current region of SGT measurements, 1/<em>f</em> noise is mainly attributed to carrier number fluctuation (CNF).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109099"},"PeriodicalIF":1.4,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143641913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-endurance bulk CMOS one-transistor cryo-memory 高耐久体积CMOS单晶体管低温存储器
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-02-28 DOI: 10.1016/j.sse.2025.109097
A. Zaslavsky , P.R. Shrestha , V.Ortiz Jimenez , J.P. Campbell , C.A. Richter
{"title":"High-endurance bulk CMOS one-transistor cryo-memory","authors":"A. Zaslavsky ,&nbsp;P.R. Shrestha ,&nbsp;V.Ortiz Jimenez ,&nbsp;J.P. Campbell ,&nbsp;C.A. Richter","doi":"10.1016/j.sse.2025.109097","DOIUrl":"10.1016/j.sse.2025.109097","url":null,"abstract":"<div><div>Previously we reported a compact one-transistor (1 T) 180 nm bulk CMOS cryo-memory with a high ≈10<sup>7</sup> <em>I</em><sub>1</sub>/<em>I</em><sub>0</sub> memory window and long ≈800 s retention time based on impact-ionization-induced charging of the transistor body. Here, we present the endurance and retention characteristics of our 1 T memory obtained from high-speed measurements at <em>T</em> = 7 K. We observe excellent endurance, with no visible degradation over 10<sup>9</sup> write ‘1′/write ‘0′ cycles. The measured retention time varies with the memory window and the leakage current, but it exceeds 10 s for a 30X <em>I</em><sub>1</sub>/<em>I</em><sub>0</sub> memory window and would be even higher in a device with no substrate contact.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109097"},"PeriodicalIF":1.4,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143563058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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