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Interlayer exchange coupling for enhanced performance in spin-transfer torque MRAM devices 层间交换耦合提高自旋传递扭矩MRAM器件的性能
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-07-07 DOI: 10.1016/j.sse.2025.109179
M. Bendra , R.L. de Orio , S. Selberherr , W. Goes , V. Sverdlov
{"title":"Interlayer exchange coupling for enhanced performance in spin-transfer torque MRAM devices","authors":"M. Bendra ,&nbsp;R.L. de Orio ,&nbsp;S. Selberherr ,&nbsp;W. Goes ,&nbsp;V. Sverdlov","doi":"10.1016/j.sse.2025.109179","DOIUrl":"10.1016/j.sse.2025.109179","url":null,"abstract":"<div><div>We present a micromagnetic modeling study that explores the impact of interface exchange coupling in multilayered spintronic devices, such as the spin-transfer torque magnetoresistive random access memory, which is at the forefront of nonvolatile storage. By examining the exchange interactions facilitated by non-magnetic or insulating layers between ferromagnetic ones, we explore the critical role of interlayer exchange coupling in the magnetic stability and domain dynamics essential for the efficiency of spin-transfer torque mechanisms. This understanding is crucial for enhancing device performance, particularly in terms of data reliability and access speeds, amid the ongoing miniaturization trend in nanotechnology. The magnetic tunnel junction within spin-transfer torque magnetoresistive random access memory, featuring a CoFeB-based layered structure, enables significant data density improvements through reduced cell sizes and enhanced magnetic properties. However, miniaturization also raises concerns about the reliability and stability of these devices, particularly due to phenomena like back-hopping. Our research addresses these concerns by highlighting the role of IEC in achieving magnetic alignment and optimizing overall device performance, thereby meeting the rigorous requirements of modern memory applications and paving the way for the next generation of memory technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109179"},"PeriodicalIF":1.4,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144596193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Superimposed two-contact gate stacks for an improved electrostatic control of Si spin qubits 用于改进硅自旋量子比特静电控制的叠加双触点栅极堆
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-06-30 DOI: 10.1016/j.sse.2025.109178
B. Martinez , B. Bertrand , Y.-M. Niquet , M. Vinet
{"title":"Superimposed two-contact gate stacks for an improved electrostatic control of Si spin qubits","authors":"B. Martinez ,&nbsp;B. Bertrand ,&nbsp;Y.-M. Niquet ,&nbsp;M. Vinet","doi":"10.1016/j.sse.2025.109178","DOIUrl":"10.1016/j.sse.2025.109178","url":null,"abstract":"<div><div>Spin qubits based on gate-defined quantum dots require a tight electrostatic control all along the active layer. Large-scale multi-qubit devices must enable an individual control over the tunnel coupling of neighbor QD pairs to perform two-qubit gates and spin readout. Here we propose a small modification of the widely used TiN/Polysilicon gate stack that offers an extra required control knob for the tunnel coupling while preserving the gate pitch. We define the relevant metrics for the tunnel control, perform 3D device simulations coupled to a toy model to optimize the device layout, and demonstrate that such a gate stack represents a scalable building block for large-scale one-dimensional spin qubit arrays.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109178"},"PeriodicalIF":1.4,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144522970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hot carrier stress in junctionless gate-all-around nMOSFETs under different bias conditions 不同偏置条件下无结栅栅型nmosfet的热载流子应力
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-06-29 DOI: 10.1016/j.sse.2025.109187
Wen-Teng. Chang , Liang-I. Cai , Hung-Hsi Chen , Jen-Chien Li , Yao-Jen Lee
{"title":"Hot carrier stress in junctionless gate-all-around nMOSFETs under different bias conditions","authors":"Wen-Teng. Chang ,&nbsp;Liang-I. Cai ,&nbsp;Hung-Hsi Chen ,&nbsp;Jen-Chien Li ,&nbsp;Yao-Jen Lee","doi":"10.1016/j.sse.2025.109187","DOIUrl":"10.1016/j.sse.2025.109187","url":null,"abstract":"<div><div>In conventional long-channel MOSFETs, the most significant hot carrier degradation at inversion-mode junctions typically occurs when the gate voltage (V<sub>GS</sub>) is approximately half the drain voltage (V<sub>DS</sub>). This work investigates the impact of different V<sub>GS</sub>/V<sub>DS</sub> ratios (1:2, 1:1, and 2:1) on the electrical stress behavior of Junctionless Gate-All-Around (JLGAA) nMOSFETs. Unlike inversion-mode devices, JLGAA transistors exhibit more pronounced threshold voltage (V<sub>t</sub>) shifts under V<sub>GS</sub>/V<sub>DS</sub> ratios of 1:1 and 2:1 compared to 1:2, especially over longer stress durations. Interestingly, the 1:2 stress condition reveals a V<sub>t</sub> turnaround effect during the early stages of stress. TCAD simulations support these observations, showing that a 2:1 V<sub>GS</sub>/V<sub>DS</sub> ratio generates a stronger electric field across the gate oxide compared to other bias conditions.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109187"},"PeriodicalIF":1.4,"publicationDate":"2025-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144569742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-loss RF substrate compatible with FD-SOI integration using Si+ implantation 使用Si+注入与FD-SOI集成兼容的低损耗射频衬底
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-06-27 DOI: 10.1016/j.sse.2025.109189
M. Perrosé , P. Acosta , J. Lugo-Alvarez , A.M. Papon , X. Garros , J.P. Raskin
{"title":"Low-loss RF substrate compatible with FD-SOI integration using Si+ implantation","authors":"M. Perrosé ,&nbsp;P. Acosta ,&nbsp;J. Lugo-Alvarez ,&nbsp;A.M. Papon ,&nbsp;X. Garros ,&nbsp;J.P. Raskin","doi":"10.1016/j.sse.2025.109189","DOIUrl":"10.1016/j.sse.2025.109189","url":null,"abstract":"<div><div>The fabrication of localized passivation layers combining Si<sup>+</sup> ion implantation and thermal annealing was explored. Using metallic coplanar waveguides, key performance metrics such as harmonic distortion and effective resistivity were extracted and analyzed. We demonstrated that the post-implantation thermal annealing temperature had a significant impact on Radio-Frequency performances. The optimum RF performances were obtained at an annealing temperature of 600 °C. This behavior was explained with photoluminescence and TEM characterization that revealed the presence of interstitial clusters. As it can be used locally, this method should enable the co-integration of Fully Depleted Silicon-on-Insulator (FD-SOI) technology with high-quality RF circuitry, leveraging the advantageous HR properties of the base Si substrate.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109189"},"PeriodicalIF":1.4,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144514018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thin dielectric to dielectric hydrophilic wafer bonding for FD-SOI and C-FET manufacturing 用于FD-SOI和C-FET制造的薄介电到介电亲水性晶圆键合
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-06-27 DOI: 10.1016/j.sse.2025.109188
P. Noel , V. Larrey , S. Tardif , F. Rieutord , D. Landru , F. Fournel
{"title":"Thin dielectric to dielectric hydrophilic wafer bonding for FD-SOI and C-FET manufacturing","authors":"P. Noel ,&nbsp;V. Larrey ,&nbsp;S. Tardif ,&nbsp;F. Rieutord ,&nbsp;D. Landru ,&nbsp;F. Fournel","doi":"10.1016/j.sse.2025.109188","DOIUrl":"10.1016/j.sse.2025.109188","url":null,"abstract":"<div><div>Direct hydrophilic bonding of silicon structures with low dielectric thickness may lead to the generation of bonding voids during annealing. Yet, silicon layer transfer requires thinner dielectric layers for FD–SOI and C-FET advanced devices. The aim being high bond strengths and low bonding void densities for advanced technological nodes, we show the crucial impact of bonding layer properties on interface sealing and bonding energies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109188"},"PeriodicalIF":1.4,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144500845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhancing the mobility of p-type SnOx thin-film transistors through doping and plasma treatment 通过掺杂和等离子体处理提高p型SnOx薄膜晶体管的迁移率
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-06-25 DOI: 10.1016/j.sse.2025.109181
Zhong Pan , Yeojin Jeong , MengMeng Chu , Yunhui Jang , Fucheng Wang , Jingwen Chen , Yong-Sang Kim , Jang-Kun Song , Muhammad Quddamah Khokhar , Junsin Yi
{"title":"Enhancing the mobility of p-type SnOx thin-film transistors through doping and plasma treatment","authors":"Zhong Pan ,&nbsp;Yeojin Jeong ,&nbsp;MengMeng Chu ,&nbsp;Yunhui Jang ,&nbsp;Fucheng Wang ,&nbsp;Jingwen Chen ,&nbsp;Yong-Sang Kim ,&nbsp;Jang-Kun Song ,&nbsp;Muhammad Quddamah Khokhar ,&nbsp;Junsin Yi","doi":"10.1016/j.sse.2025.109181","DOIUrl":"10.1016/j.sse.2025.109181","url":null,"abstract":"<div><div>P-type semiconductors are less common than their n-type counterparts, and their performance often lags in comparison, which hinders the efficiency of electronic devices. In this study, we demonstrate a two-step approach to enhance the performance of tin oxide based thin-film transistors (TFTs) by combining aluminum (Al) doping and hydrogen plasma treatment. The Al doping significantly enhanced the field-effect mobility of the SnO<sub>x</sub> films, while the hydrogen plasma treatment enabled the transition to p-type conductivity. The fabricated p-type Al-doped SnO<sub>x</sub> TFTs exhibited a threshold voltage of −5.2 V, a field-effect mobility of 1.17 cm<sup>2</sup>/V·s, and I<sub>on</sub>/I<sub>off</sub> of 10<sup>5</sup>. This work provides a novel strategy for optimizing the performance of p-type SnO<sub>x</sub> semiconductors, contributing to the development of low-power complementary metal-oxide semiconductor (CMOS) technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109181"},"PeriodicalIF":1.4,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144502114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-aligned nitrogen doping via plasma treatment of NiO/β-Ga2O3 heterojunction diodes 等离子体处理NiO/β-Ga2O3异质结二极管的自对准氮掺杂
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-06-25 DOI: 10.1016/j.sse.2025.109182
Dongbin Kim , Jongsu Baek , Yoonho Choi , Junghun Kim , Hyoung Woo Kim , Byung Jin Cho
{"title":"Self-aligned nitrogen doping via plasma treatment of NiO/β-Ga2O3 heterojunction diodes","authors":"Dongbin Kim ,&nbsp;Jongsu Baek ,&nbsp;Yoonho Choi ,&nbsp;Junghun Kim ,&nbsp;Hyoung Woo Kim ,&nbsp;Byung Jin Cho","doi":"10.1016/j.sse.2025.109182","DOIUrl":"10.1016/j.sse.2025.109182","url":null,"abstract":"<div><div>In this work, we demonstrate a novel doping process via self-aligned nitrogen (SA-N<sub>2</sub>) plasma treatment of the NiO/β-Ga<sub>2</sub>O<sub>3</sub> heterojunction diodes. The SA-N<sub>2</sub> plasma-treated heterojunction diodes exhibit improved breakdown voltage from 1080 V to 1731 V while maintaining a high on–off ratio (<em>I<sub>ON</sub>/I<sub>OFF</sub></em>) exceeding 10<sup>11</sup> and achieving a reduced specific on-resistance (<em>R<sub>on.sp</sub></em>). It is found that the SA-N<sub>2</sub> plasma treatment forms a resistive region acting as a shallow guard ring in the β-Ga<sub>2</sub>O<sub>3</sub> around the anode. It is also confirmed that doped N plays the role of both a shallow acceptor and a deep acceptor in NiO and β-Ga<sub>2</sub>O<sub>3</sub>, respectively. This process can be easily and cost-effectively applied to the heterojunction structure, contributing to further performance improvement of the wide bandgap power device.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109182"},"PeriodicalIF":1.4,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144491937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Quantum simulations of MoS2 field effect transistors including contact effects 二硫化钼场效应晶体管的量子模拟，包括接触效应
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-06-23 DOI: 10.1016/j.sse.2025.109162
A. Sanchez-Soares , T. Kelly , S.-K. Su , E. Chen , G. Fagas , J.C. Greer
{"title":"Quantum simulations of MoS2 field effect transistors including contact effects","authors":"A. Sanchez-Soares ,&nbsp;T. Kelly ,&nbsp;S.-K. Su ,&nbsp;E. Chen ,&nbsp;G. Fagas ,&nbsp;J.C. Greer","doi":"10.1016/j.sse.2025.109162","DOIUrl":"10.1016/j.sse.2025.109162","url":null,"abstract":"<div><div>Two-dimensional (2D) materials have attracted considerable interest for use as channel material in field-effect transistors (FETs) due to their potential for high packing densities and efficient electrostatic control. However, achieving low contact resistances remains a significant challenge for integrated circuit manufacture. This study presents a methodology that enables device simulations explicitly including the effects of contact stacks within a quantum mechanical framework. A means for optimizing device structures including contact effects is demonstrated and validated against experimental and <em>ab initio</em> data for metal–semimetal–semiconductor contacts for optimizing source/drain resistance in monolayer molybdenum disulfide (ML-MoS<sub>2</sub>) FETs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109162"},"PeriodicalIF":1.4,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144631986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytic model for organic field-effect transistors based on Vissenberg-Matters mobility model 基于Vissenberg-Matters迁移率模型的有机场效应晶体管解析模型
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-06-21 DOI: 10.1016/j.sse.2025.109183
Qian Bo-Han, Sun Jiu-Xun, Wei Chan, Li Yang, Cui Hai-Juan, Yang Hong-Chun
{"title":"Analytic model for organic field-effect transistors based on Vissenberg-Matters mobility model","authors":"Qian Bo-Han,&nbsp;Sun Jiu-Xun,&nbsp;Wei Chan,&nbsp;Li Yang,&nbsp;Cui Hai-Juan,&nbsp;Yang Hong-Chun","doi":"10.1016/j.sse.2025.109183","DOIUrl":"10.1016/j.sse.2025.109183","url":null,"abstract":"<div><div>The fundamental <em>I</em>–<em>V</em> formula of an organic field effect transistor (OFET) is reformulated as double integral of mobility function by using the Poisson’s equation. The reformulated <em>I</em>–<em>V</em> formula overcome the divergence of the integrand in original <em>I</em>–<em>V</em> formula and is convenient not only for further analytic derivations but also for numerical calculations. An analytic binomial expansion for arbitrary power is proposed to analytically derive the OFET model based on Vissenberg-Matters (VM) mobility model being able to consider all terms deduced from the completed VM model. The numerical calculations for six OFET made of four kinds of materials show that the matching degree between theoretical <em>I</em>–<em>V</em> curves and the experimental data is satisfactory for completed model, but evident deviations for <em>I<sub>D</sub></em>–<em>V<sub>D</sub></em> curves exhibited in usual treatment that only considering first term deduced from the VM model. It is important to consider all terms in modelling OFET to ensure accuracy and reliability for extraction of parameters. These are useful for practical applications and device simulations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109183"},"PeriodicalIF":1.4,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144471777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces 3xdd容限电源轨ESD箝位电路，用于负混合电压接口
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-06-21 DOI: 10.1016/j.sse.2025.109185
Hao-En Cheng , Ching-Lin Wu , Chun-Yu Lin
{"title":"3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces","authors":"Hao-En Cheng ,&nbsp;Ching-Lin Wu ,&nbsp;Chun-Yu Lin","doi":"10.1016/j.sse.2025.109185","DOIUrl":"10.1016/j.sse.2025.109185","url":null,"abstract":"<div><div>In this article, a novel power-rail ESD clamp circuit for negative voltage power pins has been proposed and fabricated in a 0.18-μm 1.8-V CMOS process. The proposed circuit, implemented using only 1.8-V nMOS/pMOS devices, achieves a voltage tolerance of 3xVDD (5.4 V), surpassing the 2xVDD-tolerance of most existing designs. Additionally, the circuit demonstrates HBM robustness of over 8 kV and exhibits an exceptionally low leakage current of approximately 0.7nA at room temperature, making it highly suitable for negative voltage environments in biomedical circuits, mixed-voltage applications, and power management systems.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109185"},"PeriodicalIF":1.4,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144365787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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