Solid-state Electronics最新文献_第8页

Design and modeling of resonant tunneling transport-controlled voltage-induced double quantum dot channel nanowire field-effect-transistor (DQD-FET) for multi-threshold current levels 多阈值电流水平下共振隧道输运控制电压感应双量子点通道纳米线场效应晶体管（DQD-FET）的设计与建模

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-10-01 DOI: 10.1016/j.sse.2025.109259

N. Paul , S. Chattopadhyay

{"title":"Design and modeling of resonant tunneling transport-controlled voltage-induced double quantum dot channel nanowire field-effect-transistor (DQD-FET) for multi-threshold current levels","authors":"N. Paul , S. Chattopadhyay","doi":"10.1016/j.sse.2025.109259","DOIUrl":"10.1016/j.sse.2025.109259","url":null,"abstract":"<div><div>The article deals with the modeling of gate voltage controlled resonant tunneling transport in a complementary-metal–oxide–semiconductor (CMOS) compatible double quantum dot channel nanowire field-effect-transistor (FET). Appropriate applied voltages at two separate gates, gate-1 and gate-2 of the device form two voltage-tunable quantum dots underneath the gates, within the nanowire channel. The quantum dot eigenstates are tuned by varying the applied gate voltages to enable voltage-modulated resonant tunneling transport. Such transport is modeled by employing a Schrödinger-Poisson self-consistent framework using non-equilibrium Green’s function (NEGF) formalism. Electron–phonon scattering within the nanowire channel is also considered. The transfer characteristics exhibit multiple current thresholds in the range of 10<sup>−4</sup> μA/μm–1 μA/μm due to resonant tunneling. The phonon scattering is observed to significantly depend on nanowire geometry and applied gate voltages, with tunneling dominated quasi-ballistic transport occurring at higher gate voltages. Also, steep sub-threshold slopes of 30 mV/decade–8 mV/decade range and transconductance in the range of 10<sup>−7</sup> μS/μm–1 μS/μm at room temperature are obtained by varying the nanowire diameter in the range of 20 nm–5 nm. Therefore, such device architecture exhibits significant potential for achieving multi-current thresholds in a CMOS compatible architecture at room temperature.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109259"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Frequency-driven dielectric analysis of ultrathin HfOx-TiOx composite films 超薄HfOx-TiOx复合薄膜的频率驱动介电分析

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-08-22 DOI: 10.1016/j.sse.2025.109220

Rezwana Sultana , Karimul Islam , Piotr Jeżak , Robert Mroczyński

{"title":"Frequency-driven dielectric analysis of ultrathin HfOx-TiOx composite films","authors":"Rezwana Sultana , Karimul Islam , Piotr Jeżak , Robert Mroczyński","doi":"10.1016/j.sse.2025.109220","DOIUrl":"10.1016/j.sse.2025.109220","url":null,"abstract":"<div><div>This study investigates the frequency-dependent dielectric properties of ultrathin HfO<sub>x</sub>-TiO<sub>x</sub> composite films (HTO) in a metal–oxide–semiconductor (MOS) configuration over a frequency range of 1 kHz to 3 MHz. The films were deposited using a pulsed-DC magnetron sputtering technique in an atomic layer deposition-like manner, incorporating very thin TiO<sub>x</sub> layers within the bulk of HfO<sub>x</sub>. Structural analysis revealed that the films are amorphous and exhibit uniform and smooth surfaces. The dielectric constant (<em>ε</em>′) and dielectric loss (<em>ε</em>′′) exhibit a decreasing trend with increasing frequency, demonstrating typical dielectric behavior. Furthermore, the characteristic dielectric relaxation frequency shifts toward lower frequency values with the insertion of TiO<sub>x</sub>. The Cole-Cole plot confirms the non-Debye relaxation behavior across all samples. Optical spectroscopy analysis reveals a systematic increase in the optical band gap upon more TiO<sub>x</sub> insertion. Analysis of current–voltage (I-V) characteristics demonstrates low leakage currents across the composite films. Understanding the dielectric parameters and the electrical characteristics is crucial for the potential application of these films in advanced electronic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109220"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144908456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing ultra-thin-barrier AlGaN/GaN HEMTs with LPCVD SiN passivation for high-power applications 利用LPCVD SiN钝化技术增强超薄势垒AlGaN/GaN hemt的高功率应用

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-10-02 DOI: 10.1016/j.sse.2025.109260

Jui-Sheng Wu , Chen-Hsi Tsai , You-Chen Weng , Edward Yi Chang

引用次数: 0

Comparison of Self-Heating effect between SOI and SOS MOSFETs SOI和SOS mosfet自热效应比较

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-09-18 DOI: 10.1016/j.sse.2025.109250

Run-Song Dou , Jia-Min Li , Fan-Yu Liu , Hui-ping Zhu , Bo Li , Jiang-Jiang Li , Bao-Gang Sun , Yang Huang , Jing Wan , Yong Xu , Zheng-sheng Han , Sorin Cristoloveanu

{"title":"Comparison of Self-Heating effect between SOI and SOS MOSFETs","authors":"Run-Song Dou , Jia-Min Li , Fan-Yu Liu , Hui-ping Zhu , Bo Li , Jiang-Jiang Li , Bao-Gang Sun , Yang Huang , Jing Wan , Yong Xu , Zheng-sheng Han , Sorin Cristoloveanu","doi":"10.1016/j.sse.2025.109250","DOIUrl":"10.1016/j.sse.2025.109250","url":null,"abstract":"<div><div>In this research, we perform an in-depth analysis of the self-heating effect (SHE) and heat transfer characteristics of devices fabricated on silicon-on-insulator (SOI) and silicon-on-silicon carbide (SOS) substrates using technology computer-aided design (TCAD) numerical simulations. The results reveal that, under identical operating conditions, the maximum lattice temperature increase in SOI devices is approximately 3.9 times higher than that in SOS devices, highlighting the superior thermal management properties of SOS devices. When SHE is considered at a gate voltage of 1.8 V, the leakage current in SOS devices decreases by about 27 % compared to SOI devices, demonstrating enhanced resistance to SHE in SOS devices. Analysis of the thermal dissipation pathways reveals that for SOI devices, heat primarily dissipates through the source and drain regions within the device layer, while for SOS devices it predominantly dissipates through the silicon carbide substrate due to its high thermal conductivity, thereby significantly improving thermal dissipation efficiency. Additionally, our research uncovers a correlation between increasing device layer thickness and elevated lattice temperature for both SOI and SOS structures. This phenomenon is closely associated with thermal-electric coupling effects and changes in device thermal resistance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109250"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145096281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Boosting the electrical performance of solar cells by using PIN diode structure with different layout styles controlled by MOS capacitor 利用MOS电容控制不同布局风格的PIN二极管结构提高太阳能电池的电性能

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-08-23 DOI: 10.1016/j.sse.2025.109217

Fernando Pizzo Ribeiro, Egon H.S. Galembeck, Salvador Pinillos Gimenez

引用次数: 0

ZnPc-based schottky diodes: Effect of amorphous polymer interlayers on electrical and structural properties zno基肖特基二极管：非晶聚合物中间层对电学和结构性能的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-09-16 DOI: 10.1016/j.sse.2025.109249

Nargis Khatun , Sumona Sinha , A.K.M. Maidul Islam

{"title":"ZnPc-based schottky diodes: Effect of amorphous polymer interlayers on electrical and structural properties","authors":"Nargis Khatun , Sumona Sinha , A.K.M. Maidul Islam","doi":"10.1016/j.sse.2025.109249","DOIUrl":"10.1016/j.sse.2025.109249","url":null,"abstract":"<div><div>This study investigates the influence of Indium Tin Oxide (ITO) electrode surface modification on the electrical properties of zinc phthalocyanine (ZnPc)– based Schottky diodes, using amorphous polymers, specifically polystyrene (Ps) and poly(butyl methacrylate) (PBMA). Devices with configurations of Al (Aluminum)/ZnPc/ITO, Al/ZnPc/Ps/ITO, and Al/ZnPc/PBMA/ITO were fabricated and analysed through current–voltage (I-V) characterisation. Devices modified with polymers showed significantly improved electrical performance, with the rectification ratio rising from 0.81 (pure ZnPc) to 4.24 for ITO modified with PBMA and 6.32 for ITO modified with Ps, along with optimised ideality factors and reduced series resistance. Space-charge-limited conduction (SCLC) became dominant, indicating enhanced charge mobility in the modified devices. UV–Vis analysis further confirmed this improvement, showing that PBMA modification enhances π–π* interactions and molecular aggregation within ZnPc thin films, reducing the optical bandgap from 3.05 eV to 2.75 eV (Ps) and 2.68 eV (PBMA), which indicates modified electronic properties due to polymer incorporation. Structural investigations employing XRR and AFM complement these findings, demonstrating improved crystallite size and a smoother surface, which lead to better charge transport. These results highlight the efficiency of polymer surface modification in enhancing ZnPc-based Schottky diodes, presenting intriguing possibilities for future optoelectronic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109249"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145109137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Trap-rich high-resistivity silicon for improved on-chip monolithic transformers characteristics 用于改善片上单片变压器特性的富阱高电阻硅

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-10-08 DOI: 10.1016/j.sse.2025.109261

Najeh Zeidi , Farès Tounsi , Jean-Pierre Raskin , Denis Flandre

{"title":"Trap-rich high-resistivity silicon for improved on-chip monolithic transformers characteristics","authors":"Najeh Zeidi , Farès Tounsi , Jean-Pierre Raskin , Denis Flandre","doi":"10.1016/j.sse.2025.109261","DOIUrl":"10.1016/j.sse.2025.109261","url":null,"abstract":"<div><div>This paper investigates the performance of monolithic on-chip planar transformers implemented on high-resistivity substrates incorporating a trap-rich layer (HR-Si + TR), using both experimental measurements and electromagnetic simulations. Two transformer topologies, i.e., interleaved and concentric, were fabricated, measured, and simulated on both standard silicon (Std-Si) and HR-Si + TR to assess the impact of substrate losses. Key figures of merit, including self-resonant frequency (SRF), mutual inductance, reactive and resistive coupling factors, and maximum power-transfer efficiency, were extracted and compared. Results show that the HR-Si + TR substrate markedly enhances both topologies: for the interleaved transformer, the SRF increases by 3.8 % from 3.66 to 3.80 GHz, while the peak power-transfer efficiency nearly doubles from 0.33 at 1.42 GHz to 0.63 at 2.26 GHz; for the concentric transformer, the SRF rises by over 31 % from 3.12 to 4.10 GHz, and the efficiency increases more than threefold from 0.06 at 1.48 GHz to 0.22 at 2.15 GHz. These improvements arise from the HR-Si + TR substrate’s ability to substantially reduce the resistive mutual coupling factor by minimizing eddy current losses in the substrate and raising the impedance of the RC leakage path to ground, thereby limiting trace crosstalk and power leakage between traces. The benefits are particularly pronounced in the concentric topology, where the larger winding separation amplifies the impact of reduced substrate-induced losses.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109261"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CMOS back-end-of-line integration of bilayer ferroelectric tunnel junction in 1-transistor-1-capacitor circuit 一晶体管一电容电路中双层铁电隧道结的CMOS后端集成

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-09-23 DOI: 10.1016/j.sse.2025.109255

Keerthana Shajil Nair , Muhammad Hamid Raza , Catherine Dubourdieu , Veeresh Deshpande

引用次数: 0

On the role of power dissipation in the Post-BD behavior of FDSOI NanoWire FETs 功率损耗对FDSOI纳米线场效应管后bd行为的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-08-29 DOI: 10.1016/j.sse.2025.109228

R. Goyal, A. Crespo-Yepes, M. Porti, R. Rodriguez, M. Nafria

引用次数: 0

A Schottky barrier field-effect transistor platform with variable Ge content on SOI SOI上可变锗含量的肖特基势垒场效应晶体管平台

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-08-23 DOI: 10.1016/j.sse.2025.109221

Andreas Fuchsberger , Lukas Wind , Aníbal Pacheco-Sanchez , Johannes Aberl , Moritz Brehm , Lilian Vogl , Peter Schweizer , Masiar Sistani , Walter M. Weber

引用次数: 0