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Interface roughness in Resonant Tunnelling Diodes for physically unclonable functions 物理不可克隆功能的共振隧道二极管的界面粗糙度
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-05-07 DOI: 10.1016/j.sse.2025.109131
Pranav Acharya, Vihar Georgiev
{"title":"Interface roughness in Resonant Tunnelling Diodes for physically unclonable functions","authors":"Pranav Acharya,&nbsp;Vihar Georgiev","doi":"10.1016/j.sse.2025.109131","DOIUrl":"10.1016/j.sse.2025.109131","url":null,"abstract":"<div><div>Resonant Tunnelling Diodes with Interface Roughness (IR) were investigated for their potential as components of Physically Uncloneable Functions (PUFs). A comparison of an RTD with IR, against a ‘smooth’ device without IR, showed a reduction in current and Peak to Valley Current Ratio (PVCR) between the resonant peak and valley currents <span><math><mrow><msub><mrow><mi>I</mi></mrow><mrow><mi>r</mi></mrow></msub><mo>/</mo><msub><mrow><mi>I</mi></mrow><mrow><mi>v</mi></mrow></msub></mrow></math></span>. Furthermore, IR resulted in a perturbation of the Negative Differential Region (NDR) of the IV characteristic to higher bias. This perturbation was due to IR effectively thickening barriers and thereby narrowing the Quantum Well (QW) and leading to a higher ground state QW energy. Variation of correlation length <span><math><msub><mrow><mi>L</mi></mrow><mrow><mi>C</mi></mrow></msub></math></span> and roughness asperity <span><math><msub><mrow><mi>Δ</mi></mrow><mrow><mi>R</mi><mi>M</mi><mi>S</mi></mrow></msub></math></span> for batches of 25 randomly generated RTDs with IR showed that increasing <span><math><msub><mrow><mi>Δ</mi></mrow><mrow><mi>R</mi><mi>M</mi><mi>S</mi></mrow></msub></math></span> decreased mean PVCR and increased the standard deviation of the resonant peak voltage <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>r</mi></mrow></msub></math></span> and current <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>r</mi></mrow></msub></math></span>. 150 RTDs with an <span><math><msub><mrow><mi>L</mi></mrow><mrow><mi>C</mi></mrow></msub></math></span> of 7.5 nm and <span><math><msub><mrow><mi>Δ</mi></mrow><mrow><mi>R</mi><mi>M</mi><mi>S</mi></mrow></msub></math></span> of 0.3 nm resulted in a min-entropy of 1.275 bits, showing that 100 RTDs could idealistically compose a PUF encoding 127 bits.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109131"},"PeriodicalIF":1.4,"publicationDate":"2025-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143928199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Epitaxial p+pn+ vertical short diodes for microbolometers 微辐射热计用外延p+pn+垂直短二极管
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-05-06 DOI: 10.1016/j.sse.2025.109123
R.M.R. Kubica , A. Albouy , M. Le Cocq , F. Gonzatti , F. Balestra , P. Leduc
{"title":"Epitaxial p+pn+ vertical short diodes for microbolometers","authors":"R.M.R. Kubica ,&nbsp;A. Albouy ,&nbsp;M. Le Cocq ,&nbsp;F. Gonzatti ,&nbsp;F. Balestra ,&nbsp;P. Leduc","doi":"10.1016/j.sse.2025.109123","DOIUrl":"10.1016/j.sse.2025.109123","url":null,"abstract":"<div><div>In the LWIR band, pn diodes are an attractive solution for thermometers in microbolometers. In this paper, epitaxial short <span><math><mrow><msup><mrow><mi>p</mi></mrow><mrow><mo>+</mo></mrow></msup><mi>p</mi><msup><mrow><mi>n</mi></mrow><mrow><mo>+</mo></mrow></msup></mrow></math></span> diodes were studied at 303–343 K. A <span><math><mrow><mi>T</mi><mi>C</mi><mi>C</mi></mrow></math></span> ranging from 8 %.K<span><math><msup><mrow></mrow><mrow><mo>−</mo><mn>1</mn></mrow></msup></math></span> to 3 %.K<span><math><msup><mrow></mrow><mrow><mo>−</mo><mn>1</mn></mrow></msup></math></span> between 0.2 V and 0.8 V and a current noise dominated by flicker noise were measured. Finally, at 303 K and an integration time of 40 ms, a thermal resolution ranging from 5.10<span><math><msup><mrow></mrow><mrow><mo>−</mo><mn>2</mn></mrow></msup></math></span> K to <span><math><mrow><mn>1</mn><mo>.</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>4</mn></mrow></msup></mrow></math></span> K was obtained for bias currents between <span><math><mrow><mn>5</mn><mo>.</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>11</mn></mrow></msup></mrow></math></span> A and <span><math><mrow><mn>2</mn><mo>.</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>2</mn></mrow></msup></mrow></math></span> A.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109123"},"PeriodicalIF":1.4,"publicationDate":"2025-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143936454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Excimer laser annealing of boron thin-films to fabricate large-area low-defect p+ Si regions 硼薄膜准分子激光退火制备大面积低缺陷p+ Si区
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-05-05 DOI: 10.1016/j.sse.2025.109143
Vinayak V. Hassan, Asma Attariabad, Lis K. Nanver
{"title":"Excimer laser annealing of boron thin-films to fabricate large-area low-defect p+ Si regions","authors":"Vinayak V. Hassan,&nbsp;Asma Attariabad,&nbsp;Lis K. Nanver","doi":"10.1016/j.sse.2025.109143","DOIUrl":"10.1016/j.sse.2025.109143","url":null,"abstract":"<div><div>Boron layers deposited by chemical vapor deposition at 700 °C are exposed to 308 nm excimer laser annealing (ELA). The non-annealed B-deposition is commonly used to form radiation hard p<sup>+</sup>n PureB photodiodes that have nm-shallow junction depths with low dark currents, i.e., the PureB anode region has a high Gummel number. Here a B-layer thickness ranging from a monolayer to 7 nm was studied for deposition in oxide windows to lightly-doped n-Si wafers, and diode contacting was achieved with an Al/1%Si interconnect layer. The focus was placed on a 1-nm-thin B-layer that, after ELA at fluences from 400 to 900 mJ/cm<sup>2</sup>, delivered ideal diodes with anode Gummel numbers at least as high as PureB counterparts. Fluences above 750 mJ/cm<sup>2</sup> were necessary for melting of the Si to achieve p-region sheet resistance &lt;100 Ω/sq. The maximum active doping level was 2.3 × 10<sup>21</sup> atoms/cm<sup>3</sup> in the melt zone, providing a sheet resistance of 25 Ω/sq at a junction depth of 85 nm for a fluence of 900 mJ/cm<sup>2</sup>. At 600 mJ/cm<sup>2</sup>, about a monolayer of B bonded to Si at the interface remained. This rendered a photodiode with an optimal responsivity of 0.16 A/W at 406 nm and 0.33 A/W at 670 nm wavelengths.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109143"},"PeriodicalIF":1.4,"publicationDate":"2025-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143917588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimizing unconventional trilayer SOTs for field-free switching 优化用于无场开关的非常规三层sot
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-05-02 DOI: 10.1016/j.sse.2025.109135
Nils Petter Jørstad , Wolfgang Goes , Siegfried Selberherr , Viktor Sverdlov
{"title":"Optimizing unconventional trilayer SOTs for field-free switching","authors":"Nils Petter Jørstad ,&nbsp;Wolfgang Goes ,&nbsp;Siegfried Selberherr ,&nbsp;Viktor Sverdlov","doi":"10.1016/j.sse.2025.109135","DOIUrl":"10.1016/j.sse.2025.109135","url":null,"abstract":"<div><div>The symmetry and magnitude of unconventional spin–orbit torques in ferromagnet/heavy metal/ferromagnet trilayers are investigated. Several spin-generating mechanisms are considered such as the anomalous Hall effect, anisotropic magnetoresistance, the Rashba–Edelstein effect, and the spin Hall effect. Optimal material thicknesses and magnetization configurations for maximizing out-of-plane spin torques for breaking the bilayer symmetry are presented. Furthermore, field-free switching simulations of a perpendicular SOT-MRAM utilizing the optimized trilayer torques are demonstrated, showing improved switching currents compared to another reported trilayer-based device.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109135"},"PeriodicalIF":1.4,"publicationDate":"2025-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143922457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation and investigation of high voltage CMOS device in advanced Sub-90 nm node processes 先进sub - 90nm节点制程中高压CMOS器件的实现与研究
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-04-28 DOI: 10.1016/j.sse.2025.109142
Xin Huang , Yintong Zhang , Zhaozhao Xu , Ziquan Fang , Donghua Liu , Wensheng Qian
{"title":"Implementation and investigation of high voltage CMOS device in advanced Sub-90 nm node processes","authors":"Xin Huang ,&nbsp;Yintong Zhang ,&nbsp;Zhaozhao Xu ,&nbsp;Ziquan Fang ,&nbsp;Donghua Liu ,&nbsp;Wensheng Qian","doi":"10.1016/j.sse.2025.109142","DOIUrl":"10.1016/j.sse.2025.109142","url":null,"abstract":"<div><div>The continuous scaling of MOSFET devices exacerbates short-channel effects (SCEs), such as hot-carrier injection (HCI) and threshold voltage roll-off, thereby compromising electrical performance. While lightly doped drain (LDD) processes are widely adopted in modern CMOS fabrication, conventional methods struggle to maintain performance at advanced technology nodes. This work proposes a novel high-energy LDD technology that overcomes these limitations without introducing additional fabrication complexity. Through rigorous TCAD simulations, the proposed process demonstrates enhanced device stability and improved electrical characteristics, including lower breakdown voltage variation, better threshold voltage control, and improved on/off current ratios. Benchmarked against conventional non-self-aligned (NSA) and self-aligned (SA) LDD processes, this technology offers a viable pathway for next-generation semiconductor scaling.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109142"},"PeriodicalIF":1.4,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143899261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Preliminary results on industrial 28nm FD-SOI phase change memory at cryogenic temperature 低温下工业28nm FD-SOI相变存储器的初步结果
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-04-27 DOI: 10.1016/j.sse.2025.109141
Philippe Galy , Joao Henrique Quintino Palhares , Lorena Anghel , Yann Beilliard , Fabien Alibart , Dominique Drouin , Jury Sandrini , Franck Arnaud
{"title":"Preliminary results on industrial 28nm FD-SOI phase change memory at cryogenic temperature","authors":"Philippe Galy ,&nbsp;Joao Henrique Quintino Palhares ,&nbsp;Lorena Anghel ,&nbsp;Yann Beilliard ,&nbsp;Fabien Alibart ,&nbsp;Dominique Drouin ,&nbsp;Jury Sandrini ,&nbsp;Franck Arnaud","doi":"10.1016/j.sse.2025.109141","DOIUrl":"10.1016/j.sse.2025.109141","url":null,"abstract":"<div><div>This study reports new preliminary results on fully co-integrated 28 nm FD-SOI UTBB phase change memories (PCM) programmed at room temperature (RT) and cryogenic temperature (CT). The PCM is a germanium, antimony, tellurium (GST) compound type which is found to be functional at 77K with multi-state switching without additional operating requirements compared to the ambient temperature. As the phase change memory is temperature dependent, drift tests are also performed to track the change in resistance over time after programming the pulses to estimate drift coefficients. An interesting feature is that using the same programming bias conditions, the drift coefficient is three times lower at 77K with an improvement in the I<sub>on</sub>/I<sub>off</sub> ratio. These results are very encouraging and open the door to the PCM in applications both at high temperatures (e.g. automotive) and at very low temperatures (e.g. space, quantum).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109141"},"PeriodicalIF":1.4,"publicationDate":"2025-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143904377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation into the impact of source-drain series resistance on electrical parameters of AlGaN/GaN high electron mobility transistors 源漏串联电阻对高电子迁移率AlGaN/GaN晶体管电学参数影响的研究
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-04-26 DOI: 10.1016/j.sse.2025.109138
Eduardo Canga Panzo , Nilton Graziano , Eddy Simoen , Maria Glória Caño de Andrade
{"title":"Investigation into the impact of source-drain series resistance on electrical parameters of AlGaN/GaN high electron mobility transistors","authors":"Eduardo Canga Panzo ,&nbsp;Nilton Graziano ,&nbsp;Eddy Simoen ,&nbsp;Maria Glória Caño de Andrade","doi":"10.1016/j.sse.2025.109138","DOIUrl":"10.1016/j.sse.2025.109138","url":null,"abstract":"<div><div>This research investigates the impact of source-drain series resistance (R<sub>SD</sub>) AlGaN/GaN high-electron-mobility transistors (HEMTs). Initially, the influence of R<sub>SD</sub> was analyzed in devices with varying geometries (Length and width; L<sub>g</sub> and W) as well as in devices with identical dimensions but fabricated using different gate metal manufacturing techniques. Subsequently, the effect of R<sub>SD</sub> on key parameters, including carrier mobility (μ<sub>n</sub>), effective mobility (<span><math><msub><mi>μ</mi><mrow><mi>eff</mi></mrow></msub></math></span>) and field effect mobility (<span><math><msub><mi>μ</mi><mrow><mi>FE</mi></mrow></msub></math></span>), drain current (<span><math><msub><mi>I</mi><mi>d</mi></msub></math></span>), output conductance (<span><math><msub><mi>g</mi><mi>d</mi></msub></math></span>), transconductance (<span><math><msub><mi>g</mi><mi>m</mi></msub></math></span>), threshold voltage (<span><math><msub><mi>V</mi><mi>T</mi></msub></math></span>) and subthreshold slope (<span><math><mi>S</mi></math></span>) was assessed. The results reveal that R<sub>SD</sub> tends to decrease in transistors with lower L<sub>g</sub> and higher W, highlighting a significant correlation with the channel’s geometric structure. Additionally, transistors employing different gate metal splits exhibited variations in R<sub>SD</sub>. The results further revealed that a lower R<sub>SD</sub> enhances μ<sub>n</sub>, <span><math><msub><mi>μ</mi><mrow><mi>eff</mi></mrow></msub></math></span>, <span><math><msub><mi>μ</mi><mrow><mi>FE</mi></mrow></msub></math></span>, <span><math><msub><mi>I</mi><mi>d</mi></msub></math></span>, <span><math><msub><mi>g</mi><mi>d</mi></msub></math></span>, <span><math><msub><mi>g</mi><mi>m</mi></msub></math></span>, and <span><math><mrow><mi>S</mi><mo>,</mo></mrow></math></span> while reducing <span><math><msub><mi>V</mi><mi>T</mi></msub></math></span>.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109138"},"PeriodicalIF":1.4,"publicationDate":"2025-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143899262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance of Pulse-Programmed memristive crossbar array with bimodally distributed stochastic synaptic weights 具有双峰分布随机突触权的脉冲编程记忆栅阵列的性能
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-04-24 DOI: 10.1016/j.sse.2025.109128
Nadine Dersch , Eduardo Perez , Christian Wenger , Christian Roemer , Mike Schwarz , Benjamin Iniguez , Alexander Kloes
{"title":"Performance of Pulse-Programmed memristive crossbar array with bimodally distributed stochastic synaptic weights","authors":"Nadine Dersch ,&nbsp;Eduardo Perez ,&nbsp;Christian Wenger ,&nbsp;Christian Roemer ,&nbsp;Mike Schwarz ,&nbsp;Benjamin Iniguez ,&nbsp;Alexander Kloes","doi":"10.1016/j.sse.2025.109128","DOIUrl":"10.1016/j.sse.2025.109128","url":null,"abstract":"<div><div>In this paper, we present a method of implementing memristive crossbar arrays with bimodally distributed weights. The bimodal distribution is a result of pulse-based programming. The memristive devices are used for implementing synaptic weights and can only have an ON (logical “1″) or an OFF (logical ”0″) state. The state of the memristive device after programming is determined by the bimodal distribution. The highly efficient noise-based variability approach is used to simulate this stochasticity. The memristive crossbar array is used to classify the MNIST data set and comprises more than 15,000 weights. The interpretation of these weights is investigated. In addition, the influence of the stochasticity of the weights and the accuracy of the weights on the classification results is considered and various programming settings are examined.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109128"},"PeriodicalIF":1.4,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143899936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Operation of junctionless nanowire transistors down to 4.2 Kelvin 操作低至4.2开尔文的无结纳米线晶体管
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-04-23 DOI: 10.1016/j.sse.2025.109133
F.E. Bergamaschi , J.A. Matos , M. de Souza , S. Barraud , M. Cassé , O. Faynot , M.A. Pavanello
{"title":"Operation of junctionless nanowire transistors down to 4.2 Kelvin","authors":"F.E. Bergamaschi ,&nbsp;J.A. Matos ,&nbsp;M. de Souza ,&nbsp;S. Barraud ,&nbsp;M. Cassé ,&nbsp;O. Faynot ,&nbsp;M.A. Pavanello","doi":"10.1016/j.sse.2025.109133","DOIUrl":"10.1016/j.sse.2025.109133","url":null,"abstract":"<div><div>In this work, an experimental characterization of SOI junctionless nanowire transistors operating in liquid helium temperature is conducted. DC measurements are performed in a temperature range from 300 K down to 4.2 K in devices with variable geometrical dimensions, namely the gate length and the fin width. Different electrical parameters are analyzed, such as the threshold voltage, the subthreshold slope, the low-field mobility, and the drain-induced barrier lowering (DIBL). The temperature reduction helps partially suppress short-channel effects, leading to improvement in these parameters while preserving good electrostatic control, even for highly scaled channel lengths.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109133"},"PeriodicalIF":1.4,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143882939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation on the performance limits of Dirac-source FETs 狄拉克源场效应管性能极限的研究
IF 1.4 4区 物理与天体物理
Solid-state Electronics Pub Date : 2025-04-23 DOI: 10.1016/j.sse.2025.109124
Tommaso Ugolini, Elena Gnani
{"title":"Investigation on the performance limits of Dirac-source FETs","authors":"Tommaso Ugolini,&nbsp;Elena Gnani","doi":"10.1016/j.sse.2025.109124","DOIUrl":"10.1016/j.sse.2025.109124","url":null,"abstract":"<div><div>In this work, we develop a two-dimensional (2D) simulation tool addressing Poisson’s equation within the semiconductor section of a 2D Dirac source (DS) field-effect transistor under the assumption of ballistic transport. Next, we compute the current curves using the WKB approximation for the calculation of the transmission probability. The current turns out to be quite sensitive to the tunneling probability at the graphene-semiconductor heterojunction. Different gate-insulating materials and gate lengths are considered with the aim of identifying any possible limitations in the performance of DS-FETs. The obtained results highlight some important issues, while confirming that a minimum subthreshold swing (SS) of 40 mV/dec can be achieved and that SS values below 60 mV/dec can be extended up to three and a half decades.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"228 ","pages":"Article 109124"},"PeriodicalIF":1.4,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143882882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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