Solid-state Electronics最新文献_第9页

Analysis and 3D TCAD simulations of single-qubit control in an industrially-compatible FD-SOI device 工业兼容 FD-SOI 器件中的单量子比特控制分析和 3D TCAD 仿真

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-23 DOI: 10.1016/j.sse.2024.108883

Pericles Philippopoulos , Félix Beaudoin , Philippe Galy

引用次数: 0

Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology 通过实验设计方法评估薄片电阻，优化钛自排列硅化物形成过程

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-17 DOI: 10.1016/j.sse.2024.108879

In-Chi Gau , Yao-Wen Chang , Giin-Shan Chen , Yi-Lung Cheng , Jau-Shiung Fang

{"title":"Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology","authors":"In-Chi Gau , Yao-Wen Chang , Giin-Shan Chen , Yi-Lung Cheng , Jau-Shiung Fang","doi":"10.1016/j.sse.2024.108879","DOIUrl":"10.1016/j.sse.2024.108879","url":null,"abstract":"<div><p>A low-resistivity titanium silicide (TiSi<sub>2</sub>) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi<sub>2</sub>. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi<sub>2</sub> by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi<sub>2</sub>. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 10<sup>14</sup> cm<sup>−2</sup>. The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"215 ","pages":"Article 108879"},"PeriodicalIF":1.7,"publicationDate":"2024-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139922999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mechanisms of negative bias instability of commercial SiC MOSFETs observed by current transients 通过瞬态电流观察商用碳化硅 MOSFET 负偏压不稳定性的机理

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-16 DOI: 10.1016/j.sse.2024.108880

Mayank Chaturvedi , Daniel Haasmann , Philip Tanner , Sima Dimitrijev

{"title":"Mechanisms of negative bias instability of commercial SiC MOSFETs observed by current transients","authors":"Mayank Chaturvedi , Daniel Haasmann , Philip Tanner , Sima Dimitrijev","doi":"10.1016/j.sse.2024.108880","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108880","url":null,"abstract":"<div><p>This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results reveal that near-interface traps (NITs) with energy levels aligned to the valence band trap holes from the valence band by tunneling, which is different from published results about NITs with energy levels aligned to the energy gap. The impact of the aluminium implantation process of the p-type region on hole trapping is also demonstrated. The presented analysis also reveals that the hole trapping by NITs is limited to the p-type region, indicating that the aluminium implantation process is responsible for the detected NITs.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"215 ","pages":"Article 108880"},"PeriodicalIF":1.7,"publicationDate":"2024-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0038110124000297/pdfft?md5=8b64cf1c8febd3253cd38f2decbe16c0&pid=1-s2.0-S0038110124000297-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139901416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K 300 K 至 4 K nMOS Forksheets 阵列的直流性能和低频噪声表征

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-16 DOI: 10.1016/j.sse.2024.108881

R. Asanovski , A. Grill , J. Franco , P. Palestri , H. Mertens , R. Ritzenthaler , N. Horiguchi , B. Kaczer , L. Selmi

{"title":"Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K","authors":"R. Asanovski , A. Grill , J. Franco , P. Palestri , H. Mertens , R. Ritzenthaler , N. Horiguchi , B. Kaczer , L. Selmi","doi":"10.1016/j.sse.2024.108881","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108881","url":null,"abstract":"<div><p>The DC and low-frequency noise performance of an array of 800 parallel Forksheet MOSFETs were investigated by performing measurements over a wide temperature range from 300 K to 4 K. The array structure allowed to measure a representative average performance of the devices and provided a large effective area for 1/f noise analysis. Results showed an improvement in the saturation drain current when going from room temperature to cryogenic temperatures, with the subthreshold swing saturating around 100 K and the threshold voltage shifting by approximately 150 mV, following similar trends observed in Silicon cryogenic electronics. Additionally, the study confirms that the noise at cryogenic temperatures does not follow the commonly assumed linear scaling with temperature. This deviation from the linear scaling has been associated with the presence of tail states at the interface in bulk and silicon-on-insulator (SOI) devices. These results suggest that the excess 1/f noise in this advanced device architecture is not related to the device architecture but rather to the microscopic material properties of semiconductor/dielectric interfaces.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"215 ","pages":"Article 108881"},"PeriodicalIF":1.7,"publicationDate":"2024-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0038110124000303/pdfft?md5=7de7cf19f9aa802c05bf38babf13afe8&pid=1-s2.0-S0038110124000303-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139908196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-frequency noise characterization of positive bias stress effect on the spatial distribution of trap in β-Ga2O3 FinFET 低频噪声表征正偏压对 β-Ga2O3 FinFET 中陷阱空间分布的影响

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-15 DOI: 10.1016/j.sse.2024.108882

Hagyoul Bae , Geon Bum Lee , Jaewook Yoo , Khwang-Sun Lee , Ja-Yun Ku , Kihyun Kim , Jungsik Kim , Peide D. Ye , Jun-Young Park , Yang-Kyu Choi

引用次数: 0

Impact of passivation layer on the subthreshold behavior of p-type CuO accumulation-mode thin-film transistors 钝化层对 p 型氧化铜积层模式薄膜晶体管阈下行为的影响

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-13 DOI: 10.1016/j.sse.2024.108878

Qi Chen, Xi Zeng, Denis Flandre

引用次数: 0

Experimental study of time-dependent dielectric degradation by means of random telegraph noise spectroscopy 通过随机电报噪声光谱法对随时间变化的介电降解进行实验研究

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-08 DOI: 10.1016/j.sse.2024.108877

Nishant Saini , Davide Tierno , Kristof Croes , Valeri Afanas’ev , Jan Van Houdt

{"title":"Experimental study of time-dependent dielectric degradation by means of random telegraph noise spectroscopy","authors":"Nishant Saini , Davide Tierno , Kristof Croes , Valeri Afanas’ev , Jan Van Houdt","doi":"10.1016/j.sse.2024.108877","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108877","url":null,"abstract":"<div><p>Time-dependent dielectric breakdown (TDDB) is commonly used to assess dielectric failures. However, TDDB provides limited insights into the physics of dielectric degradation. In this paper, we explore the potential of random telegraph noise (RTN) spectroscopy to study the physics of dielectric breakdown. RTN is a fluctuation in the dielectric leakage current due to capture/emission of injected electrons by dielectric traps. We report an RTN study of large-area alumina (<span><math><mrow><msub><mrow><mtext>Al</mtext></mrow><mrow><mn>2</mn></mrow></msub><msub><mrow><mtext>O</mtext></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span>) thin films. A stress experiment is performed on a fresh sample, where RTN is measured before, during and after stress. Important degradation signatures are identified in the RTN spectra. The degradation imposed by the applied stress is observed as a consistent transition between two distributions, where the RTN transitions from an initial pre-stress Gaussian, to a final post-stress exponential. A calculation of the noise entropy, which generally increases with growing material disorder, confirms the transition to an exponential distribution. Finally, we relate the RTN distribution parameters to the defectivity of the dielectric.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"214 ","pages":"Article 108877"},"PeriodicalIF":1.7,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139732473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

First-principles screening for sustainable OTS materials 可持续 OTS 材料的第一原理筛选

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-03 DOI: 10.1016/j.sse.2024.108876

S. Clima , D. Matsubayashi , T. Ravsher , D. Garbin , R. Delhougne , G.S. Kar , G. Pourtois

引用次数: 0

Hot-carrier induced degradation of Ge/STI interfaces in Ge-on-Si junction devices 硅结 Ge 器件中 Ge/STI 接口的热载流子诱导降解

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-02 DOI: 10.1016/j.sse.2024.108867

Solomon Musibau , Jacopo Franco , Artemisia Tsiara , Ingrid De Wolf , Kristof Croes

引用次数: 0

Characterization of trap density in Indium-Gallium-Zinc-Oxide thin films by admittance measurements in multi-finger MOS structures 通过多指 MOS 结构中的导纳测量表征氧化铟镓锌薄膜中的陷阱密度

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-02-01 DOI: 10.1016/j.sse.2024.108866

Hongwei Tang , Attilio Belmonte , Dennis Lin , Valeri Afanas'ev , Patrick Verdonck , Adrian Chasin , Harold Dekkers , Romain Delhougne , Jan Van Houdt , Gouri Sankar Kar

引用次数: 0