Solid-state Electronics最新文献_第9页

Proposed equivalent circuit physics-based model of InP based double heterojunction bipolar transistors 基于物理的 InP 双异质结双极晶体管等效电路模型提案

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-07-02 DOI: 10.1016/j.sse.2024.108979

Tao Liu , Gang Wu , Yongqing Huang , Taoxiang Yang , Xiuhua Zeng , Meiling Shi , Huijuan Niu , Wenjing Fang

引用次数: 0

Impedance sensors based on silicon-carbon films for detection low concentrations of organic vapors 基于硅碳薄膜的阻抗传感器用于检测低浓度有机蒸汽

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-07-02 DOI: 10.1016/j.sse.2024.108978

Tatiana S. Mikhailova, Rajathsing Kalusulingam, Inna Yu. Bogush, Tatiana N. Myasoedova

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A unified explicit charge-based capacitance model for metal oxide thin-film transistors 基于电荷的金属氧化物薄膜晶体管统一显式电容模型

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-06-29 DOI: 10.1016/j.sse.2024.108976

Fei-fan Li , Hao-yang Li , Zhao-hua Zhou , Lei Zhou , Wan-ling Deng , Miao Xu , Lei Wang , Wei-jing Wu , Jun-biao Peng

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Determination of source series resistances for InP HEMT under normal bias condition 确定正常偏置条件下 InP HEMT 的源串联电阻

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-06-26 DOI: 10.1016/j.sse.2024.108975

Ao Zhang , Jianjun Gao

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Study of ISFET for KCl sensing 用于氯化钾传感的 ISFET 研究

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-06-21 DOI: 10.1016/j.sse.2024.108974

Pedro H. Duarte , Ricardo C. Rangel , Katia R.A. Sasaki , Joao A. Martino

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Editorial “Selected papers from the international conference on simulation of semiconductor processes and devices 2022” 编辑 "2022 年国际半导体工艺和设备模拟会议论文选"

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-06-12 DOI: 10.1016/j.sse.2024.108973

Francisco Gamiz, Carlos Sampedro, Luca Donetti, Carlos Navarro

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Switching layer optimization in Co-based CBRAM for >105 memory window in sub-100 µA regime 优化钴基 CBRAM 中的开关层，在低于 100 µA 的条件下实现 >105 内存窗口

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-06-06 DOI: 10.1016/j.sse.2024.108964

Yongjun Cho , Bo Soo Kang , Pankaj Kumbhare , Romain Delhougne , Laura Nyns , Ming Mao , Ludovic Goux , Gouri Sankar Kar , Attilio Belmonte

引用次数: 0

Investigation on MOS shunt LVTSCR for ESD application 有关用于 ESD 应用的 MOS 分流 LVTSCR 的研究

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-05-28 DOI: 10.1016/j.sse.2024.108963

Dongyan Zhao , Yipeng Chen , Shicong Zhou , Xinyu Zhu , Yidong Yuan , Yi Hu , Tianting Zhao , Xiaojuan Li , Shurong Dong

{"title":"Investigation on MOS shunt LVTSCR for ESD application","authors":"Dongyan Zhao , Yipeng Chen , Shicong Zhou , Xinyu Zhu , Yidong Yuan , Yi Hu , Tianting Zhao , Xiaojuan Li , Shurong Dong","doi":"10.1016/j.sse.2024.108963","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108963","url":null,"abstract":"<div><p>Continuously scaling down ICs result in more stringent electrostatic discharge (ESD) protection design requirements. Compared with other devices, silicon-controlled rectifier (SCR) has become the first choice for its area efficiency and robustness. In order to improve the latch-up issue of SCR, various schemes have been proposed. A simple method is to extend the SCR path length, which will result in the enlarged ON resistance. Segment technology is also used to improve the holding voltage of SCR, but it will shrink the effective emitter area and lead to the serious degradation of ESD robustness. MS-LVTSCR is used to protect CMOS input ports. The circuit operating voltage is 3.3V and the gate oxide DC breakdown voltage is 19V so that considering the safety margin, the ESD window is from 3.63V to 17.1V. This work proposes a novel MOS shunt low-voltage trigger silicon-controlled rectifier (MS-LVTSCR) electrostatic discharge protection device by inserting an embedded PMOS structure. Compared with the conventional LVTSCR, the proposed MS-LVTSCR achieves 53% improvement in the holding voltage and still maintains high ESD robustness with a current level of 31.5 mA/<span><math><mi>μ</mi></math></span>m without more device area consumption. In addition, both the TCAD simulation and theoretical analysis were carried out to explore the principle of current shunt effect to improve holding voltage. The extra shunt paths will weaken the conductance modulation effect of the main drift region in the main SCR path and its holding voltage can be further raised by reducing the proportion of main drift region current in the total current. We also conducted detailed studies on the mechanisms and geometry effects of this newly proposed structure via experimental validations.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"218 ","pages":"Article 108963"},"PeriodicalIF":1.7,"publicationDate":"2024-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141243499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electron and spin transport in semiconductor and magnetoresistive devices 半导体和磁阻器件中的电子和自旋传输

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-05-23 DOI: 10.1016/j.sse.2024.108962

Viktor Sverdlov , Siegfried Selberherr

{"title":"Electron and spin transport in semiconductor and magnetoresistive devices","authors":"Viktor Sverdlov , Siegfried Selberherr","doi":"10.1016/j.sse.2024.108962","DOIUrl":"10.1016/j.sse.2024.108962","url":null,"abstract":"<div><p>As the scaling of CMOS-based technology shows signs of an imminent saturation, employing the second intrinsic electron characteristics – the electron spin – is attractive to further boost the performance of integrated circuits and to introduce new computational paradigms. The spin promises to offer an additional functionality to charge-based CMOS circuitry. Spin injection and spin manipulation by gate-induced electrics field at room temperatures were successfully demonstrated in semiconductor channels, expectations that such spin-driven devices appear in digital circuits to complement or even replace CMOS become credible.</p><p>On the memory side, the nonvolatile CMOS-compatible spin-transfer torque (STT) and the spin–orbit torque magnetoresistive random access memories (MRAMs) are already competing with flash memory and even SRAM for embedded applications.</p><p>To accurately model spin and charge transport and torques in magnetic tunnel junctions, we innovatively extend the spin and charge transport equations to multi-layered structures consisting of normal and ferromagnetic metal layers separated by tunnel barriers. We validate our approach by modeling the magnetization dynamics in ultra-scaled MRAM cells. A multi-bit operation is predicted in an MRAM cell with a composite free layer.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"218 ","pages":"Article 108962"},"PeriodicalIF":1.7,"publicationDate":"2024-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141132307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Temperature- and variability-aware compact modeling of ferroelectric FDSOI FET for memory and emerging applications 用于存储器和新兴应用的铁电 FDSOI FET 的温度和变异感知紧凑建模

IF 1.7 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-05-17 DOI: 10.1016/j.sse.2024.108954

Swetaki Chatterjee , Shubham Kumar , Amol Gaidhane , Chetan Kumar Dabhi , Yogesh Singh Chauhan , Hussam Amrouch

{"title":"Temperature- and variability-aware compact modeling of ferroelectric FDSOI FET for memory and emerging applications","authors":"Swetaki Chatterjee , Shubham Kumar , Amol Gaidhane , Chetan Kumar Dabhi , Yogesh Singh Chauhan , Hussam Amrouch","doi":"10.1016/j.sse.2024.108954","DOIUrl":"10.1016/j.sse.2024.108954","url":null,"abstract":"<div><p>In this paper, we present a temperature and variability-aware Verilog-A-based compact model for simulating Ferroelectric FET. The model captures the rich physics of ferroelectric materials and the important electrical characteristics, such as the history effect, the impact of pulse width and amplitude on threshold voltage, and temperature-dependent degradation of polarization. The impact of variability is also explored regarding reliable operation of the FeFET. The developed model is robust and can accurately capture the experimentally observed trends, such as the change in polarization due to temperature, increased memory window on reading from the back-gate, etc. Further, we discuss two applications of our developed model viz. (a) multi-level-cell storage and (b) FeFET-based array for MAC operations. The designs are tested using the proposed model in commercial SPICE simulator at different temperatures including the effect of variation. Analysis presented in this article reveals that variability and temperature can be detrimental for operation of FeFET-based systems.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"218 ","pages":"Article 108954"},"PeriodicalIF":1.7,"publicationDate":"2024-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141051822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0