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Low-frequency noise characterization of positive bias stress effect on the spatial distribution of trap in β-Ga2O3 FinFET 低频噪声表征正偏压对 β-Ga2O3 FinFET 中陷阱空间分布的影响
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-02-15 DOI: 10.1016/j.sse.2024.108882
Hagyoul Bae , Geon Bum Lee , Jaewook Yoo , Khwang-Sun Lee , Ja-Yun Ku , Kihyun Kim , Jungsik Kim , Peide D. Ye , Jun-Young Park , Yang-Kyu Choi
{"title":"Low-frequency noise characterization of positive bias stress effect on the spatial distribution of trap in β-Ga2O3 FinFET","authors":"Hagyoul Bae ,&nbsp;Geon Bum Lee ,&nbsp;Jaewook Yoo ,&nbsp;Khwang-Sun Lee ,&nbsp;Ja-Yun Ku ,&nbsp;Kihyun Kim ,&nbsp;Jungsik Kim ,&nbsp;Peide D. Ye ,&nbsp;Jun-Young Park ,&nbsp;Yang-Kyu Choi","doi":"10.1016/j.sse.2024.108882","DOIUrl":"10.1016/j.sse.2024.108882","url":null,"abstract":"<div><p>The reliability of a <em>β</em>-Ga<sub>2</sub>O<sub>3</sub> thin-film field-effect transistor is investigated under positive-bias stress (PBS). The transistor has a tri-gate structure with a gate dielectric of Al<sub>2</sub>O<sub>3</sub>. By characterizing low-frequency noise (LFN), the spatial distribution of trap in the gate dielectric was quantitatively extracted. The measured power spectral density (PSD) followed a 1/f-shape due to trapping and de-trapping of the channel carriers to and from the gate dielectric. Notably, the vertical distribution of the traps perpendicular to the interface of <em>β</em>-Ga<sub>2</sub>O<sub>3</sub> and Al<sub>2</sub>O<sub>3</sub> was mapped</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139878210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of passivation layer on the subthreshold behavior of p-type CuO accumulation-mode thin-film transistors 钝化层对 p 型氧化铜积层模式薄膜晶体管阈下行为的影响
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-02-13 DOI: 10.1016/j.sse.2024.108878
Qi Chen, Xi Zeng, Denis Flandre
{"title":"Impact of passivation layer on the subthreshold behavior of p-type CuO accumulation-mode thin-film transistors","authors":"Qi Chen,&nbsp;Xi Zeng,&nbsp;Denis Flandre","doi":"10.1016/j.sse.2024.108878","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108878","url":null,"abstract":"<div><p>In this work, models of p-type CuO metal-oxide- semiconductor (MOS) capacitor and thin-film transistors (TFTs) are established using numerical simulation tools and compared with experimental data, to investigate the impact of a passivation layer on the TFT subthreshold behavior. Simulated transfer curves and hole concentrations of back-gated CuO TFT with 10 μm channel length confirm the experimental observation of buried-channel and accumulation-mode conduction mechanisms. The subthreshold behavior is analyzed with HfO2 passivation on the top CuO surface varying the densities of fixed oxide charge and interface states, as well as the thickness of the CuO film. The simulation results demonstrate a significant potential improvement of the subthreshold slope and on/off current ratio, mainly thanks to the optimization of the fixed oxide charge densities.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139744379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental study of time-dependent dielectric degradation by means of random telegraph noise spectroscopy 通过随机电报噪声光谱法对随时间变化的介电降解进行实验研究
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-02-08 DOI: 10.1016/j.sse.2024.108877
Nishant Saini , Davide Tierno , Kristof Croes , Valeri Afanas’ev , Jan Van Houdt
{"title":"Experimental study of time-dependent dielectric degradation by means of random telegraph noise spectroscopy","authors":"Nishant Saini ,&nbsp;Davide Tierno ,&nbsp;Kristof Croes ,&nbsp;Valeri Afanas’ev ,&nbsp;Jan Van Houdt","doi":"10.1016/j.sse.2024.108877","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108877","url":null,"abstract":"<div><p>Time-dependent dielectric breakdown (TDDB) is commonly used to assess dielectric failures. However, TDDB provides limited insights into the physics of dielectric degradation. In this paper, we explore the potential of random telegraph noise (RTN) spectroscopy to study the physics of dielectric breakdown. RTN is a fluctuation in the dielectric leakage current due to capture/emission of injected electrons by dielectric traps. We report an RTN study of large-area alumina (<span><math><mrow><msub><mrow><mtext>Al</mtext></mrow><mrow><mn>2</mn></mrow></msub><msub><mrow><mtext>O</mtext></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span>) thin films. A stress experiment is performed on a fresh sample, where RTN is measured before, during and after stress. Important degradation signatures are identified in the RTN spectra. The degradation imposed by the applied stress is observed as a consistent transition between two distributions, where the RTN transitions from an initial pre-stress Gaussian, to a final post-stress exponential. A calculation of the noise entropy, which generally increases with growing material disorder, confirms the transition to an exponential distribution. Finally, we relate the RTN distribution parameters to the defectivity of the dielectric.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139732473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
First-principles screening for sustainable OTS materials 可持续 OTS 材料的第一原理筛选
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-02-03 DOI: 10.1016/j.sse.2024.108876
S. Clima , D. Matsubayashi , T. Ravsher , D. Garbin , R. Delhougne , G.S. Kar , G. Pourtois
{"title":"First-principles screening for sustainable OTS materials","authors":"S. Clima ,&nbsp;D. Matsubayashi ,&nbsp;T. Ravsher ,&nbsp;D. Garbin ,&nbsp;R. Delhougne ,&nbsp;G.S. Kar ,&nbsp;G. Pourtois","doi":"10.1016/j.sse.2024.108876","DOIUrl":"10.1016/j.sse.2024.108876","url":null,"abstract":"<div><p>Chalcogenides Ovonic Threshold Switching (OTS) chalcogenide materials have suitable electronic properties for two-terminal selector application. To reduce the use of toxic elements, there is a need to replace As and Se of the presently-used OTS materials with environmentally friendly OTS materials. In an effort to accelerate the discovery of such materials, we predicted electrical device parameters only from atomistic first-principles simulations and performed a theoretical screening for alternative OTS compositions. With the help of the identified correlations between the theoretical trap/mobility gaps, the local atomic coordination environments and the experimentally-measured threshold, hold voltages or hold, leakage currents and other physics-based material parameter filters like material stability and OTS gauge, we identified more than 35 promising As/Se-free ternary alloy OTS compositions.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139680029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hot-carrier induced degradation of Ge/STI interfaces in Ge-on-Si junction devices 硅结 Ge 器件中 Ge/STI 接口的热载流子诱导降解
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-02-02 DOI: 10.1016/j.sse.2024.108867
Solomon Musibau , Jacopo Franco , Artemisia Tsiara , Ingrid De Wolf , Kristof Croes
{"title":"Hot-carrier induced degradation of Ge/STI interfaces in Ge-on-Si junction devices","authors":"Solomon Musibau ,&nbsp;Jacopo Franco ,&nbsp;Artemisia Tsiara ,&nbsp;Ingrid De Wolf ,&nbsp;Kristof Croes","doi":"10.1016/j.sse.2024.108867","DOIUrl":"10.1016/j.sse.2024.108867","url":null,"abstract":"<div><p>The degradation of Ge junctions epitaxially grown within shallow trench isolation (STI) on Si is investigated for geometries with different Area-to-Perimeter (A/P) ratios under constant-voltage stress. We show that the reverse-bias relative current shift (<span><math><mrow><mi>Δ</mi><mi>I</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>/</mo><msub><mrow><mi>I</mi></mrow><mrow><mn>0</mn></mrow></msub></mrow></math></span>) exhibits a two component behaviour ascribed to the interplay between charge trapping in (pre-existing) traps and generation of new defects mostly along the perimeter of the junctions (Ge/STI interfaces), which affect the trap assisted tunnelling (TAT) leakage current. A semi-empirical model of the degradation kinetics is proposed, allowing to decouple the role of the two individual degradation mechanisms. The insights and the methodology presented are expected to be of relevance for Ge-on-Si active components for Silicon Photonics applications.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139661911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of trap density in Indium-Gallium-Zinc-Oxide thin films by admittance measurements in multi-finger MOS structures 通过多指 MOS 结构中的导纳测量表征氧化铟镓锌薄膜中的陷阱密度
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-02-01 DOI: 10.1016/j.sse.2024.108866
Hongwei Tang , Attilio Belmonte , Dennis Lin , Valeri Afanas'ev , Patrick Verdonck , Adrian Chasin , Harold Dekkers , Romain Delhougne , Jan Van Houdt , Gouri Sankar Kar
{"title":"Characterization of trap density in Indium-Gallium-Zinc-Oxide thin films by admittance measurements in multi-finger MOS structures","authors":"Hongwei Tang ,&nbsp;Attilio Belmonte ,&nbsp;Dennis Lin ,&nbsp;Valeri Afanas'ev ,&nbsp;Patrick Verdonck ,&nbsp;Adrian Chasin ,&nbsp;Harold Dekkers ,&nbsp;Romain Delhougne ,&nbsp;Jan Van Houdt ,&nbsp;Gouri Sankar Kar","doi":"10.1016/j.sse.2024.108866","DOIUrl":"10.1016/j.sse.2024.108866","url":null,"abstract":"<div><p>We perform trap density (D<sub>t</sub>) extraction through admittance measurements on amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin films using multi-finger MOS structures. We investigate the impact of channel length (L<sub>ch</sub>) on C-V and G-V characteristics and demonstrate a reliable trap density extraction method in short channel devices. The method is validated for pure and Magnesium-doped a-IGZO (Mg:IGZO). The experimental results are consistent with simulations based on a distributed network model.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139661909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures 全面评估在高温下工作的 SOI 叠层纳米线 nMOSFET 中的栅极诱导漏极泄漏
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-02-01 DOI: 10.1016/j.sse.2024.108865
Michelly de Souza , Antonio Cerdeira , Magali Estrada , Mikaël Cassé , Sylvain Barraud , Maud Vinet , Olivier Faynot , Marcelo A. Pavanello
{"title":"Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures","authors":"Michelly de Souza ,&nbsp;Antonio Cerdeira ,&nbsp;Magali Estrada ,&nbsp;Mikaël Cassé ,&nbsp;Sylvain Barraud ,&nbsp;Maud Vinet ,&nbsp;Olivier Faynot ,&nbsp;Marcelo A. Pavanello","doi":"10.1016/j.sse.2024.108865","DOIUrl":"10.1016/j.sse.2024.108865","url":null,"abstract":"<div><p>This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139662158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Preconditioning of Ohmic p-GaN power HEMT for reproducible Vth measurements 预调节欧姆 p-GaN 功率 HEMT 以实现可重现的 Vth 测量
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-01-30 DOI: 10.1016/j.sse.2024.108868
L. Ghizzo , D. Trémouilles , F. Richardeau , G. Guibaud
{"title":"Preconditioning of Ohmic p-GaN power HEMT for reproducible Vth measurements","authors":"L. Ghizzo ,&nbsp;D. Trémouilles ,&nbsp;F. Richardeau ,&nbsp;G. Guibaud","doi":"10.1016/j.sse.2024.108868","DOIUrl":"10.1016/j.sse.2024.108868","url":null,"abstract":"<div><p>The fluctuation of the threshold voltage (<em>V<sub>th</sub></em>) presents a challenge while monitoring electrical drift in reliability studies of GaN HEMTs. While technologies, such as ohmic p-GaN, may lessen <em>V<sub>th</sub></em> fluctuations, the issue of recoverable charge trapping still remains. Therefore, it is crucial to adopt novel characterization methods when conducting reliability studies, in order to measure intrinsic changes rather than the charge-trapping effects that exist even in non-degraded transistors. One method expounded in this paper allows for a reliable and replicable measurement of <em>V<sub>th</sub></em> for an ohmic p-GaN gate HEMT GaN. A dedicated gate-bias profile is introduced immediately prior to the threshold-voltage measurement to stabilize it. This preconditioning phase necessitates a negative bias voltage followed by a suitably high voltage to be effective. The novel protocol introduced is also shown to be applicable to other HEMT GaN structures.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139648194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of gate-source/drain overlap on FeFETs 栅源/漏极重叠对 FeFET 的影响
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-01-26 DOI: 10.1016/j.sse.2024.108862
Changha Kim , Dong-Oh Kim , Woo Young Choi
{"title":"Influence of gate-source/drain overlap on FeFETs","authors":"Changha Kim ,&nbsp;Dong-Oh Kim ,&nbsp;Woo Young Choi","doi":"10.1016/j.sse.2024.108862","DOIUrl":"10.1016/j.sse.2024.108862","url":null,"abstract":"<div><p>The influences of gate-source/drain overlap on ferroelectric field-effect transistors (FeFETs) are investigated with various gate-source/drain overlap lengths (<em>L</em><sub>ov</sub>’s) and doping concentrations of the gate-source/drain overlap region (<em>D</em><sub>ov</sub>’s). In contrast to conventional metal-ferroelectric-insulator-semiconductor (MFIS) FeFETs, a metal layer between a ferroelectric and an insulator layer allows overlap capacitance to affect the entire ferroelectric layer in metal-ferroelectric-metal–insulator-semiconductor (MFMIS) FeFETs. As <em>L</em><sub>ov</sub> and <em>D</em><sub>ov</sub> increase, the effective channel length of both FeFETs decreases. In the case of MFMIS FeFETs, the gate-to-source/drain overlap capacitance (<em>C</em><sub>ov,gate-S/D</sub>) increases, leading to a larger voltage drop across the ferroelectric layer. According to the simulation results, MFMIS FeFETs show a wider memory window (MW) and larger sensing margin than MFIS FeFETs.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139583903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved electrical performance of InAlN/GaN high electron mobility transistors with forming gas annealing 通过成型气体退火提高 InAlN/GaN 高电子迁移率晶体管的电气性能
IF 1.7 4区 物理与天体物理
Solid-state Electronics Pub Date : 2024-01-19 DOI: 10.1016/j.sse.2024.108861
Siheng Chen , Peng Cui , Handoko Linewih , Kuan Yew Cheong , Mingsheng Xu , Xin Luo , Liu Wang , Jiuji Sun , Jiacheng Dai , Jisheng Han , Xiangang Xu
{"title":"Improved electrical performance of InAlN/GaN high electron mobility transistors with forming gas annealing","authors":"Siheng Chen ,&nbsp;Peng Cui ,&nbsp;Handoko Linewih ,&nbsp;Kuan Yew Cheong ,&nbsp;Mingsheng Xu ,&nbsp;Xin Luo ,&nbsp;Liu Wang ,&nbsp;Jiuji Sun ,&nbsp;Jiacheng Dai ,&nbsp;Jisheng Han ,&nbsp;Xiangang Xu","doi":"10.1016/j.sse.2024.108861","DOIUrl":"10.1016/j.sse.2024.108861","url":null,"abstract":"<div><p>The surface electronic states and defects of gallium nitride based high-electron-mobility transistors (HEMTs) play a critical role affecting channel electron density, electron mobility, leakage current, radio frequency (RF) power output and power added efficiency of devices. This article demonstrates the improved surface properties of InAlN/GaN HEMTs through forming gas (FG) annealing, resulting in a significantly improved electrical properties. The X-ray photoelectron spectra reveals a reduction of surface native oxide after FG H<sub>2</sub>/N<sub>2</sub> annealing whereby the amount of Ga–O bonds is decreased. Compared with N<sub>2</sub> annealing, an on-resistance of 1.68 Ω·mm, a subthreshold swing of 118 mV/dec, a transconductance peak of 513 mS/mm, a gate diode breakdown voltage of surpassing 42 V, and a high current/power gain cutoff frequency (<em>f</em><sub>T</sub>/<em>f</em><sub>max</sub>) of 165/165 GHz are achieved by the 50-nm InAlN/GaN HEMT on Si substrate.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2024-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139509548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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