Solid-state Electronics最新文献_第9页

A Schottky barrier field-effect transistor platform with variable Ge content on SOI SOI上可变锗含量的肖特基势垒场效应晶体管平台

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-08-23 DOI: 10.1016/j.sse.2025.109221

Andreas Fuchsberger , Lukas Wind , Aníbal Pacheco-Sanchez , Johannes Aberl , Moritz Brehm , Lilian Vogl , Peter Schweizer , Masiar Sistani , Walter M. Weber

引用次数: 0

Layout effects on the thermal metrics of multichannel FinFETs 布局对多通道finfet热度量的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-09-12 DOI: 10.1016/j.sse.2025.109229

Lisa Tondelli , Andries J. Scholten , Thanh Viet Dinh , Luca Selmi

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Physics-based compact model of subband energy for GAAFETs including corner rounding and geometric variability analysis utilizing Monte Carlo simulation 基于物理的GAAFETs子带能量紧凑模型，包括角化和利用蒙特卡罗模拟的几何变异性分析

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-09-30 DOI: 10.1016/j.sse.2025.109253

Swapna Sarker, Abhishek Kumar, Avirup Dasgupta

引用次数: 0

Statistical enhancement in two-particle Device Monte Carlo 蒙特卡罗双粒子器件的统计增强

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-08-26 DOI: 10.1016/j.sse.2025.109210

Josef Gull, Hans Kosina

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Silicon nanowire field-effect transistor biosensors with bowtie antenna 带领结天线的硅纳米线场效应晶体管生物传感器

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-09-06 DOI: 10.1016/j.sse.2025.109230

Yongqiang Zhang , Kai Li , Nazarii Boichuk , Denys Pustovyi , Valeriia Chekubasheva , Hanlin Long , Mykhailo Petrychuk , Svetlana Vitusevich

{"title":"Silicon nanowire field-effect transistor biosensors with bowtie antenna","authors":"Yongqiang Zhang , Kai Li , Nazarii Boichuk , Denys Pustovyi , Valeriia Chekubasheva , Hanlin Long , Mykhailo Petrychuk , Svetlana Vitusevich","doi":"10.1016/j.sse.2025.109230","DOIUrl":"10.1016/j.sse.2025.109230","url":null,"abstract":"<div><div>In this study, we fabricated high-quality, liquid gate-all-around silicon nanowire (NW) field-effect transistor (FET) biosensors with a gold bowtie antenna using a silicon-on-insulator (SOI) wafer. The electrical and noise properties of these novel NW FETs were investigated under 940 nm light-emitting diode (LED) optical excitation in different solutions. A two-level signal (TLS) that is useful for biosensing was successfully activated at the light excitation only. The detection of repeatable fluctuations in current, manifested as minor peaks in the I–V curves under infrared illumination, confirms the activation of a TLS in the biosensors. The TLS demonstrates a linear dependence of its amplitude in relation to intensity. Moreover, we performed TLS studies in MgCl<sub>2</sub> solutions of different concentrations. The results indicate that the FET devices incorporating a gold antenna have considerable potential for the excitation of TLS, thus allowing the sensitivity of the biosensors to be about 300 % enhanced.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109230"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparative effects of plasma treatments on SiO2 surface and bonding performance for wafer and hybrid bonding 等离子体处理对硅片和杂化键合SiO2表面和键合性能的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-09-16 DOI: 10.1016/j.sse.2025.109246

Sung-Min Park , Sang Hyun Jung , Joong-Heon Kim , Seung Heon Shin , Jaejin Lee

{"title":"Comparative effects of plasma treatments on SiO2 surface and bonding performance for wafer and hybrid bonding","authors":"Sung-Min Park , Sang Hyun Jung , Joong-Heon Kim , Seung Heon Shin , Jaejin Lee","doi":"10.1016/j.sse.2025.109246","DOIUrl":"10.1016/j.sse.2025.109246","url":null,"abstract":"<div><div>We investigate the effects of plasma on SiO<sub>2</sub> surfaces in various plasma environments, including Ar, O<sub>2</sub>, and N<sub>2</sub>, under identical plasma conditions for low-temperature annealing in SiO<sub>2</sub>/SiO<sub>2</sub> wafer bonding. After plasma treatments, no damage is observed on the SiO<sub>2</sub> surface, which is comparable to post-CMP SiO<sub>2</sub>. With the Ar and O<sub>2</sub> plasma treatments and XPS analysis, the SiO<sub>2</sub> surface shows a Si-OH-rich surface and changes to more hydrophilic properties. Although N<sub>2</sub> plasma treatment results in a few isolated voids being observed compared to O<sub>2</sub> plasma treatment, N<sub>2</sub> plasma treatment will be a suitable choice for Cu/SiO<sub>2</sub> hybrid bonding thanks to its highest bonding strength compared to other plasma treatments and the ability to avoid Cu oxidation. On the other hand, O<sub>2</sub> plasma treatment on SiO<sub>2</sub> surface is the most effective way for SiO<sub>2</sub>/SiO<sub>2</sub> wafer bonding providing excellent hydrophilicity, strong bonding strength, and minimal bonding voids.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109246"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Statistical analysis of random dopant fluctuation in Complementary FET 互补场效应管中随机掺杂波动的统计分析

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-09-24 DOI: 10.1016/j.sse.2025.109254

Sandeep Kumar , Deven H. Patil , Khushi Jain , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta , Navjeet Bagga

{"title":"Statistical analysis of random dopant fluctuation in Complementary FET","authors":"Sandeep Kumar , Deven H. Patil , Khushi Jain , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta , Navjeet Bagga","doi":"10.1016/j.sse.2025.109254","DOIUrl":"10.1016/j.sse.2025.109254","url":null,"abstract":"<div><div>The vertical stacking of the confined channels (sheets) in stacked transistors requires a tightly controlled geometrical design, with doping fluctuation as a critical factor that decides the device’s reliability. Therefore, using well-calibrated TCAD models, we thoroughly investigate the impact of random dopant fluctuation (RDF) on Complementary FET (CFET). The standard deviation (σ) of threshold voltage (V<sub>th</sub>), ON current (I<sub>ON</sub>), and OFF current (I<sub>OFF</sub>) is statistically calculated with varying channel doping, source/drain (S/D) extension region (L<sub>EXT</sub>), channel thickness, channel width, and number of sheets. The comprehensive investigation indicates that a threshold fluctuation (σV<sub>th</sub>) of ∼ 2 mV is observed even in an undoped channel, which indicates that RDF is significantly pronounced in L<sub>EXT</sub>, causing reliability concerns. Thus, the proposed analysis is worth exploring for an insight into the scalability of CFET for future sub-2 nm technology nodes.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109254"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MULHACEN, enhanced multi-subband Monte Carlo simulator for nonplanar FETs 用于非平面场效应管的增强型多子带蒙特卡罗模拟器

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-08-23 DOI: 10.1016/j.sse.2025.109213

L. Donetti, C. Medina-Bailon, J.L. Padilla, C. Sampedro, F. Gamiz

引用次数: 0

Design and analysis of source-side raised SiGe storage for improved sensing margin in 1T DRAM 为提高1T DRAM的感测裕度，源端提升SiGe存储的设计与分析

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-10-09 DOI: 10.1016/j.sse.2025.109258

Geon Kim , Jin So , Eungi Hwang , Jun Lee , Garam Kim

{"title":"Design and analysis of source-side raised SiGe storage for improved sensing margin in 1T DRAM","authors":"Geon Kim , Jin So , Eungi Hwang , Jun Lee , Garam Kim","doi":"10.1016/j.sse.2025.109258","DOIUrl":"10.1016/j.sse.2025.109258","url":null,"abstract":"<div><div>As semiconductor devices scale aggressively into the nanoscale regime, one-transistor (1T) dynamic random-access memory (DRAM) has gained attention as a highly scalable alternative to conventional capacitor-based DRAM. By storing charge in the transistor’s floating body, 1T DRAM enables a compact cell design without the need for a separate storage capacitor. However, existing silicon-based 1T DRAM structures suffer from limited charge retention and degraded sensing margin, both of which restrict reliable memory operations. This work proposes a novel 1T DRAM structure featuring a SiGe hole storage region strategically raised near the source side. The SiGe region enhances hole confinement in the storage region and reduces diffusion-driven recombination at the source and drain, resulting in improved sensing performance. Technology computer-aided design (TCAD) simulations demonstrate that the proposed structure achieves up to 14 % improvement in sensing margin compared to conventional designs, along with enhanced read current differentiation. These results validate the effectiveness of the proposed approach and its suitability for next-generation, high-density, low-power memory applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109258"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Interpretation of electrical instability for polycrystalline silicon vertical TFT 多晶硅垂直TFT的电不稳定性解释

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2025-12-01 Epub Date: 2025-10-11 DOI: 10.1016/j.sse.2025.109263

Peng Zhang , Emmanuel Jacques , Régis Rogel , Laurent Pichon , Olivier Bonnaud

{"title":"Interpretation of electrical instability for polycrystalline silicon vertical TFT","authors":"Peng Zhang , Emmanuel Jacques , Régis Rogel , Laurent Pichon , Olivier Bonnaud","doi":"10.1016/j.sse.2025.109263","DOIUrl":"10.1016/j.sse.2025.109263","url":null,"abstract":"<div><div>Due to its excellent electrical performance and compatibility with CMOS processing, polycrystalline silicon TFT has been applied in AMOLED display backplane. As short channel length can potentially benefit current density and cutoff frequency, polycrystalline silicon vertical TFT can be applied in conventional 2-transistor and 1-capcitor (2T1C) pixel unit. The fabrication of polycrystalline silicon vertical TFT was introduced, and the electrical characteristics of the fabricated device was demonstrated. Thereafter, the electrical parameters of the vertical TFT were analyzed and compared under different electrical stress durations, which interprets the inherent mechanism of the stress instability. The total density of states (DOS) and interface DOS of the fabricated devices also indicate that the stress instability is due to charge trapping in gate dielectric layer. The electrical instability is simulated by using high-<em>k</em> gate dielectric layer, and the reduced electrical field in the gate dielectric layer can potentially improve the electrical stability. Finally, 2T1C configuration of AMOLED pixel unit shows the influence of gate dielectric layer on the stress stability, the TFTs with high-<em>k</em> gate dielectric layer shows higher stress stability and lower error rate of OLED current.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109263"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145320062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0