Solid-state Electronics最新文献_第9页

Influence of gate work function variations on characteristics of fin-shaped silicon quantum dot device with multi-gate under existence of gate electrostatic coupling 栅极功函数变化对存在栅极静电耦合的多栅极鳍状硅量子点器件特性的影响

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-22 DOI: 10.1016/j.sse.2024.109013

Kimihiko Kato, Hidehiro Asai, Hiroshi Oka, Shota Iizuka, Hiroshi Fuketa, Takumi Inaba, Takahiro Mori

引用次数: 0

Sputter-Deposited copper iodide thin film transistors with low Operating voltage 低工作电压的溅射沉积碘化铜薄膜晶体管

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-21 DOI: 10.1016/j.sse.2024.109014

Zachary C. Adamson , Rotem Zilberberg , Iryna Polishchuk , Natalia Thomas , Kyumin Kim , Alexander Katsman , Boaz Pokroy , Alexander Zaslavsky , David C. Paine

{"title":"Sputter-Deposited copper iodide thin film transistors with low Operating voltage","authors":"Zachary C. Adamson , Rotem Zilberberg , Iryna Polishchuk , Natalia Thomas , Kyumin Kim , Alexander Katsman , Boaz Pokroy , Alexander Zaslavsky , David C. Paine","doi":"10.1016/j.sse.2024.109014","DOIUrl":"10.1016/j.sse.2024.109014","url":null,"abstract":"<div><div>This paper reports on a back-gated p-type thin film transistor (TFT) with copper iodide (CuI) as the channel material, a HfO<sub>2</sub> gate dielectric layer, and Al<sub>2</sub>O<sub>3</sub> passivation. The γ-CuI channel was deposited from a CuI target using DC magnetron sputtering at room temperature. Our TFT can be fully shut off by V<sub>G</sub> = 4 V, with a field-effect channel hole mobility μ<sub>h</sub> ∼ 1.5–2 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>. An anneal in forming gas was performed twice, once at 200 °C, then at 250 °C to improve gate control, yielding a final I<sub>on</sub>/I<sub>off</sub> current ratio of ∼ 250. The anneal served two purposes: to reduce the oxygen acceptor density in the CuI channel and reduce the concentration of interface states between the CuI, Al<sub>2</sub>O<sub>3</sub> passivation, and HfO<sub>2</sub>. A model of the device was built in an industrial TCAD simulator, which reproduces the measured characteristics and allows an estimation of interface state densities and channel doping.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109014"},"PeriodicalIF":1.4,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142536110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced resistive switching performance in TiN/AlOx/Pt RRAM by high-temperature I-V cycling 通过高温 I-V 循环提高 TiN/AlOx/Pt RRAM 的电阻开关性能

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-15 DOI: 10.1016/j.sse.2024.109011

Tao He , Huiyu Yan , Yixuan Wang

引用次数: 0

A well-conditioned surface potential equation for dynamically depleted SOI MOS devices accounting for the front-depletion/back-accumulation operation mode 适用于动态耗尽型 SOI MOS 器件的表面电势方程（考虑了前耗尽/后积累工作模式

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-10 DOI: 10.1016/j.sse.2024.109010

Thomas Bédécarrats, Sébastien Martinie, Adrien Vaysset, Olivier Rozeau

引用次数: 0

Emission cells with quantum dots on silicon chip prepared by using fs pulsed laser 利用 fs 脉冲激光在硅芯片上制备量子点发射电池

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-10-04 DOI: 10.1016/j.sse.2024.109009

Wei-Qi Huang , Yin-lian Li , Zhong-Mei Huang , Hao-Ze Wang , Xi Zhang , Qi-Bin Liu , Shi-Rong Liu

{"title":"Emission cells with quantum dots on silicon chip prepared by using fs pulsed laser","authors":"Wei-Qi Huang , Yin-lian Li , Zhong-Mei Huang , Hao-Ze Wang , Xi Zhang , Qi-Bin Liu , Shi-Rong Liu","doi":"10.1016/j.sse.2024.109009","DOIUrl":"10.1016/j.sse.2024.109009","url":null,"abstract":"<div><div>Emission efficiency of bulk-silicon is very low due to its indirect-gap of energy band. However, it is interesting that the enhanced emission has been observed in the micro-cavities array fabricated by using femtosecond (fs) pulsed laser, in which the stimulated emission characteristics occur after annealing for suitable time in the photo-luminescence (PL) measurement at room temperature. The results of experiment and calculation demonstrated that the enhanced emission may be originated from the Si quantum dots embedded in the micro-cavities prepared by fs pulsed laser. Here, the direct-gap of energy band appears after annealing due to the Heisenberg principle related to ⊿k–1/⊿x in quantum system of nanostructures. The PL intensity obviously increases on the Si quantum dots growing with annealing for better crystallization, in which the external quantum efficiency is higher than 40 % near 760 nm. A new kind of emission source of the micro-cavities array in visible wavelength has been built on silicon wafer, in which the Si quantum dots play a main role for enhancement of emission. It should have a good application in optical integrated chip based on silicon, such as emission cells built on Si chip.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109009"},"PeriodicalIF":1.4,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142416692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A nanophotonic approach to signal-to-noise ratio of quantum dot infrared photodetectors with surface plasmonic excitation 利用表面等离子体激发量子点红外光探测器信噪比的纳米光子方法

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-09-29 DOI: 10.1016/j.sse.2024.109008

S.C. Lee

{"title":"A nanophotonic approach to signal-to-noise ratio of quantum dot infrared photodetectors with surface plasmonic excitation","authors":"S.C. Lee","doi":"10.1016/j.sse.2024.109008","DOIUrl":"10.1016/j.sse.2024.109008","url":null,"abstract":"<div><div>A nanophotonic approach to the signal-to-noise ratio (SNR) of an InAs-based quantum dot infrared photodetector (QDIP) with surface plasmonic excitation is reported. A 100 nm-thick Au film, perforated with a 3.1 μm-period, 2-dimensional square array of holes, referred to as a metal photonic crystal (MPC), is employed as a plasmonic coupler for it. Under the irradiance on the MPC integrated atop the QDIP, the fundamental surface plasma wave (SPW) is excited along their interface at ∼10.3 μm in wavelength. It carries the near-field that interacts with the quantum dots (QDs) under the interface. Depending on the presence of the coupler, the QDIP generates two different current–voltage (I-V) characteristics; one from the QDs normally working without MPC and the other from those coupled to the SPW near-field with it. The two I-V’s unfold the signal and noise current of each case with photoconductive gain. In their relation, generation-recombination and shot noises which are correlated with the detector signal current are directly affected by the plasmonic coupling but other sources including thermal noise are not relevant to it. Relying on these differences, the I-V analysis allows the SNR of each case and shows ∼20× enhancement by the plasmonic coupling. It reveals that most of the noise current is attributed to thermal fluctuations inherent to the quantum confinement of the QDIP. The SNR lower than the quantum efficiency in plasmonic enhancement is addressed.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109008"},"PeriodicalIF":1.4,"publicationDate":"2024-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142416685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Smart-CX – Method of extraction of parasitic capacitances in ICs Smart-CX - 集成电路寄生电容提取方法

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-09-26 DOI: 10.1016/j.sse.2024.109007

O.M. Grudanov , M.B. Grudanov

{"title":"Smart-CX – Method of extraction of parasitic capacitances in ICs","authors":"O.M. Grudanov , M.B. Grudanov","doi":"10.1016/j.sse.2024.109007","DOIUrl":"10.1016/j.sse.2024.109007","url":null,"abstract":"<div><div>This paper proposes a novel rule-based parasitic capacitance extraction methodology, integrated into Smart-CX, to enhance the accuracy of SPICE simulations and physical verification of ICs. This methodology is crucial during the microchip design phase, particularly in preparation for fabrication on mature to advanced process nodes. The proposed enhanced analytical method addresses the accuracy/time tradeoffs between numerical and analytical extraction techniques. This study validates the accuracy of the methodology by comparison of the extracted parasitic parameters with foundry-provided 2D-models. The parasitic capacitances that are extracted within this method include: area capacitances <span><math><mrow><mo>(</mo><mi>C</mi><mi>a</mi><mo>)</mo></mrow></math></span>, coupling capacitances (<span><math><mrow><mi>C</mi><mi>c</mi><mo>)</mo></mrow></math></span>, including via-to-via capacitances <span><math><mrow><mo>(</mo><mi>C</mi><mi>m</mi><mi>v</mi><mo>)</mo></mrow></math></span>, contact-to-gate capacitances <span><math><mrow><mo>(</mo><mi>C</mi><mi>m</mi><mi>g</mi><mo>)</mo></mrow></math></span>, contact-to-active capacitances <strong>(</strong><span><math><mrow><mi>C</mi><mi>m</mi><mi>c</mi><mo>)</mo></mrow></math></span> and fringe type capacitances with the top <span><math><mrow><mo>(</mo><mi>C</mi><mi>f</mi><mi>t</mi><mo>)</mo></mrow></math></span> and bottom <span><math><mrow><mo>(</mo><mi>C</mi><mi>f</mi><mi>b</mi><mo>)</mo></mrow></math></span> conductive layers.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109007"},"PeriodicalIF":1.4,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142437856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced response and recovery performance of α-hexathiophene sensors for NO2 gas by dual heterogeneous interface 通过双异质界面提高α-六硫酚传感器对二氧化氮气体的响应和回收性能

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-09-19 DOI: 10.1016/j.sse.2024.109006

Kaicaiayi Kelimu, Yiqun Zhang, Yangyang Zhu, Heping Su, Xi Lu, Li Juan Wang

引用次数: 0

Carrier modulation and effective passivation of tin oxide thin-film transistors by organic surface doping 通过有机表面掺杂实现氧化锡薄膜晶体管的载流子调制和有效钝化

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-09-16 DOI: 10.1016/j.sse.2024.109005

Guoxiang Song , Xinan Zhang , Haoxuan Xu

引用次数: 0

Fine-tuning Cesium lead chloride perovskite field-effect transistors for sensing applications: Bridging numerical modeling and experimental validation 微调用于传感应用的氯化铯铅过氧化物场效应晶体管：连接数值建模与实验验证

IF 1.4 4区物理与天体物理

Solid-state Electronics Pub Date : 2024-09-12 DOI: 10.1016/j.sse.2024.109004

Gehad Ali , Reem Mahmoud , Mohamed Wafeek , Moataz M.K. Yousef , Sameh O. Abdellatif

{"title":"Fine-tuning Cesium lead chloride perovskite field-effect transistors for sensing applications: Bridging numerical modeling and experimental validation","authors":"Gehad Ali , Reem Mahmoud , Mohamed Wafeek , Moataz M.K. Yousef , Sameh O. Abdellatif","doi":"10.1016/j.sse.2024.109004","DOIUrl":"10.1016/j.sse.2024.109004","url":null,"abstract":"<div><p>This study presents a comprehensive approach to fine-tuning Cesium Lead Chloride Perovskite Field-Effect Transistors (CsPbCl<sub>3</sub>-FETs) for sensing applications by bridging numerical modeling with experimental validation. By combining finite element methods in COMSOL Multiphysics for optimization, we tailored FET parameters such as oxide and perovskite thin film thickness. The fabricated FET, with a 200 nm semiconductor layer and 30 nm oxide thickness, was strategically chosen to operate in a non-depletion mode, maximizing mobility while minimizing power consumption. Experimental results closely aligned with numerical simulations, showcasing a threshold voltage of 0.50 V±0.07 V and an impressive on/off current ratio of 1.50 x 10<sup>4</sup> ± 0.3 x 10<sup>4</sup>. Notably, the perovskite FET exhibited remarkable carrier mobility in saturation mode, reaching 5.40 cm<sup>2</sup>/V-s ± 0.8 cm<sup>2</sup>/V-s, outperforming other attempts in the literature. This work underscores the potential of CsPbCl<sub>3</sub> FETs for high-performance sensing applications, offering insights into optimizing device parameters for enhanced functionality and efficiency.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109004"},"PeriodicalIF":1.4,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142233637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0