GatedNN: An accurate deep learning-based parameter extraction for BSIM-CMG

Abstract

An enhanced deep learning (DL) -based parameter extraction method for transistor compact models, named GatedNN, is introduced. GatedNN achieves significant accuracy improvements over existing DL-based parameter extraction techniques. The innovation lies in incorporating neural network (NN) with gating mechanism and compact model-aware techniques: model parameter importance analysis and model quality check. The GatedNN uses gates to resolve optimization conflicts among model parameters by controlling gradient descent during training. The importance analysis focuses on optimizing more crucial parameters that contribute to the current curve. The model quality check cleans the training data fed to the GatedNN and ensures the robustness of the NN output. Evaluated on the BSIM-CMG model with measured FinFET data, the proposed approach demonstrates a substantial 69% error reduction compared to recently DL-based parameter extractor. Furthermore, the scalability and mathematical robustness of the generated model are tested. The proposed GatedNN also provides insights into model parameters and device characteristics, aiding in understanding and adjusting for desired characteristics. We believe the developed method can advance the development of DL-based parameter extraction.