用于FD-SOI和C-FET制造的薄介电到介电亲水性晶圆键合

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-06-27 DOI:10.1016/j.sse.2025.109188

P. Noel , V. Larrey , S. Tardif , F. Rieutord , D. Landru , F. Fournel

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引用次数: 0

摘要

低介电厚度硅结构的直接亲水性键合在退火过程中可能导致键合空洞的产生。然而，对于FD-SOI和C-FET先进器件，硅层转移需要更薄的介电层。为了使先进的技术节点具有高的键合强度和低的键合空洞密度，我们展示了键合层性能对界面密封和键合能的关键影响。

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Thin dielectric to dielectric hydrophilic wafer bonding for FD-SOI and C-FET manufacturing

Direct hydrophilic bonding of silicon structures with low dielectric thickness may lead to the generation of bonding voids during annealing. Yet, silicon layer transfer requires thinner dielectric layers for FD–SOI and C-FET advanced devices. The aim being high bond strengths and low bonding void densities for advanced technological nodes, we show the crucial impact of bonding layer properties on interface sealing and bonding energies.

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.