N-P. Tran, F. Milesi, V-H. Le, L-D. Mohgouk Zouknak, P. Dezest, Ph. Rodriguez, L. Brunet, B. Duriez, M-C. Cyrille, C. Fenouillet-Beranger
{"title":"Toward full relaxation of sSOI substrates for PFET device fabrication","authors":"N-P. Tran, F. Milesi, V-H. Le, L-D. Mohgouk Zouknak, P. Dezest, Ph. Rodriguez, L. Brunet, B. Duriez, M-C. Cyrille, C. Fenouillet-Beranger","doi":"10.1016/j.sse.2025.109196","DOIUrl":null,"url":null,"abstract":"<div><div>The new generation of 10 nm FDSOI requires more performance enhancers to increase mobility in the channels, where electron mobility is improved by tensile stress for nMOS and hole mobility is improved by compressive stress for pMOS. Therefore, strained silicon-on-insulator (sSOI) wafers are considered to improve nMOS performance. In the case of using sSOI wafers, relaxing the tensile silicon for PMOS appears to be beneficial to facilitate the Ge condensation process. In this paper, we demonstrate over 90 % relaxation from a 1.25 GPa tensile sSOI starting wafer. Multiple iterations of ion implantation and annealing are also investigated and may provide a path for further relaxation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109196"},"PeriodicalIF":1.4000,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125001418","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The new generation of 10 nm FDSOI requires more performance enhancers to increase mobility in the channels, where electron mobility is improved by tensile stress for nMOS and hole mobility is improved by compressive stress for pMOS. Therefore, strained silicon-on-insulator (sSOI) wafers are considered to improve nMOS performance. In the case of using sSOI wafers, relaxing the tensile silicon for PMOS appears to be beneficial to facilitate the Ge condensation process. In this paper, we demonstrate over 90 % relaxation from a 1.25 GPa tensile sSOI starting wafer. Multiple iterations of ion implantation and annealing are also investigated and may provide a path for further relaxation.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.