Michelly de Souza , Marcelo A. Pavanello , Mikaël Cassé , Sylvain Barraud
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引用次数: 0
Abstract
This study experimentally investigates the electrical characteristics of seven-level stacked nanosheet SOI nMOSFETs for high-temperature applications. The experimental findings reveal a significant advantage of this architecture, demonstrating a reduced threshold voltage variation with temperature compared to both two-level stacked nanosheet transistors and state-of-the-art Fully-Depleted SOI MOSFETs. Furthermore, analysis of the normalized transconductance per total width indicates that the enhancement in carrier mobility, typically observed for wider nanosheets relative to narrower ones, tends to saturate for wider devices and to reduce as the operating temperature increases. Also, the normalized transconductance per channel length indicates a reduction of mobility for short-channel devices.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.