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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers最新文献

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A 4.1mW 79dB-DR 4th-order Source-FollowerBased Continuous-Time Filter for WLAN Receivers 一种用于WLAN接收机的4.1mW 79dB-DR四阶源跟随器连续时间滤波器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696187
S. D’Amico, M. Conta, A. Baschirotto
{"title":"A 4.1mW 79dB-DR 4th-order Source-FollowerBased Continuous-Time Filter for WLAN Receivers","authors":"S. D’Amico, M. Conta, A. Baschirotto","doi":"10.1109/ISSCC.2006.1696187","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696187","url":null,"abstract":"Using a composite source-follower with positive feedback to synthesize complex poles, a single-branch CMOS biquad achieves large linearity at low overdrive voltage, saving power. In 0.18mum CMOS with a 1.8V supply, a 41h-order 10MHz filter for WLAN applications achieves 17.5dBm IIP3 and mu40dB HD3 for a 600mVpp_diff input signal amplitude. A 24muVrms noise gives a 79dB DR while drawing 2.25mA from 1.8V","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127732280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces 用于下一代存储器接口的90nm CMOS 100mW 9.6Gb/s收发器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696055
Edoardo Prete, Dirk Scheideler, A. Sanders
{"title":"A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces","authors":"Edoardo Prete, Dirk Scheideler, A. Sanders","doi":"10.1109/ISSCC.2006.1696055","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696055","url":null,"abstract":"An architecture for next-generation memory interface is demonstrated using 90nm bulk silicon to provide a 2-tap emphasized TX with <19ps jitter at 9.6Gb/s. The circuit uses a programmable PLL to track jitter up to 200MHz. The transceiver consumes 100mW from a 1V supply","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133931569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS 一种30mW 12b 40MS/s带高增益抵消正反馈放大器的90nm数字CMOS分位ADC
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696120
Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda, Akihide Ogawa
{"title":"A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS","authors":"Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda, Akihide Ogawa","doi":"10.1109/ISSCC.2006.1696120","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696120","url":null,"abstract":"A 12b 40MS/s 2-step subranging ADC is realized in a 90nm digital CMOS process. It uses a 7b coarse quantizer with a high-gain offset-canceling positive-feedback amplifier. ENOB is 10.2b at a 0.7V supply and 11.0b at a 1.0V supply. The ADC consumes 30mW at 40MS/s","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"11 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133112212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
11Gb/s monolithically integrated silicon optical receiver for 850nm wavelength 11Gb/s单片集成硅光接收器，850nm波长
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696131
R. Swoboda, H. Zimmermann
{"title":"11Gb/s monolithically integrated silicon optical receiver for 850nm wavelength","authors":"R. Swoboda, H. Zimmermann","doi":"10.1109/ISSCC.2006.1696131","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696131","url":null,"abstract":"A monolithically integrated optical receiver is realized in a modified silicon 0.5mum BiCMOS process with fT=25 GHz that contains a pin photodiode. At a wavelength of 850nm, a BER of 10-9 , a PRBS of 231-1, the receiver has sensitivities of -10.8dBm, -10.1dBm, and -8.9dBm for data rates of 8Gb/s, 10Gb/s, and 11Gb/s, respectively","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114609652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A 16-Core RISC Microprocessor with Network Extensions 具有网络扩展的16核RISC微处理器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696061
V. Yalala, D. Brasili, D. Carlson, A. Hughes, Anil K. Jain, T. Kiszely, Kolar Kodandapani, A. Varadharajan, T. Xanthopoulos
{"title":"A 16-Core RISC Microprocessor with Network Extensions","authors":"V. Yalala, D. Brasili, D. Carlson, A. Hughes, Anil K. Jain, T. Kiszely, Kolar Kodandapani, A. Varadharajan, T. Xanthopoulos","doi":"10.1109/ISSCC.2006.1696061","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696061","url":null,"abstract":"A multi-core RISC processor is integrated with a number of security engines and network function accelerators creating a high-performance power-efficient SoC. It contains 180M transistors, dissipates 25W at 600MHz and is fabricated in a 1.2V 0.13mum CMOS process with 9 layers of copper interconnect using FSG dielectric and C4 bumps","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"67 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113933113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m 耐pvt低1/f噪声双环混合锁相环，0.18/spl mu/m
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696304
Hyung-Rok Lee, Ook Kim, Keewook Jung, John Shin, D. Jeong
{"title":"A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m","authors":"Hyung-Rok Lee, Ook Kim, Keewook Jung, John Shin, D. Jeong","doi":"10.1109/ISSCC.2006.1696304","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696304","url":null,"abstract":"A dual-loop analog-digital hybrid PLL with a small-bandwidth digital loop and large-bandwidth analog loop achieves low jitter by suppressing 1/f noise and does not require off-chip loop filter components. The operating range using a narrow-range VCO is from 10 to 200MHz. The output jitter over this range is <0.028UIpp. The chip is implemented in a 0.18mum CMOS process and consumes 50mW from a 1.8V supply","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116153250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Performance Variations of a 66GHz Static CML Divider in 90nm CMOS 90nm CMOS中66GHz静态CML分频器的性能变化
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696274
J. Plouchart, Jonghae Kim, V. Karam, R. Trzcinski, J. Gross
{"title":"Performance Variations of a 66GHz Static CML Divider in 90nm CMOS","authors":"J. Plouchart, Jonghae Kim, V. Karam, R. Trzcinski, J. Gross","doi":"10.1109/ISSCC.2006.1696274","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696274","url":null,"abstract":"A 66GHz maximum operating clock frequency is measured for a 90nm CMOS static CML divide-by-2 with a 25.5mW latch power dissipation. Statistical self-oscillation frequency measurements exhibit a mean of 42.6 and 39.2GHz at 25degC and 85degC, and a 2.8GHz standard deviation. The mean dissipated power is 44.3mW at 1.4V, with a 2.2mW standard deviation","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124462202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Low Flicker-Noise Quadrature Mixer Topology 低闪烁噪声正交混频器拓扑
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696244
Rajasekhar Pullela, T. Sowlati, D. Rozenblit
{"title":"Low Flicker-Noise Quadrature Mixer Topology","authors":"Rajasekhar Pullela, T. Sowlati, D. Rozenblit","doi":"10.1109/ISSCC.2006.1696244","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696244","url":null,"abstract":"A mixer topology that improves NF at low offset frequencies by reducing 1/f noise contributions is fabricated in 0.13mum CMOS. The NF at 10kHz is 9dB, which is 9dB less than a conventional mixer. The mixer also has 2dB higher gain, improved quadrature matching, higher IP2, straightforward implemention, and is robust over PVT","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124857642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A 20Gb/s Embedded Clock Transceiver in 90nm CMOS 20Gb/s嵌入式时钟收发器在90nm CMOS
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696181
B. Casper, J. Jaussi, F. O’Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, R. Mooney
{"title":"A 20Gb/s Embedded Clock Transceiver in 90nm CMOS","authors":"B. Casper, J. Jaussi, F. O’Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, R. Mooney","doi":"10.1109/ISSCC.2006.1696181","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696181","url":null,"abstract":"A forwarded clock I/O link in 90nm CMOS is capable of passing data at 20Gb/s over 7-inches of FR4 with 2 sockets and packages at a power dissipation of less than 12mW/Gb/s. Passive distribution and AC coupling of the forwarded clock are used to achieve 820 fsrms of sample-time uncertainty. Nyquist rate channel losses in excess of -15dB are compensated using a combination of 4-tap transmit equalization and receiver continuous-time equalization","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122059227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link 用于芯片间时钟和数据链路的1Tb/s 3W电感耦合收发器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696223
N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, T. Kuroda
{"title":"A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link","authors":"N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, T. Kuroda","doi":"10.1109/ISSCC.2006.1696223","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696223","url":null,"abstract":"A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122139985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
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