A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m

Abstract

A dual-loop analog-digital hybrid PLL with a small-bandwidth digital loop and large-bandwidth analog loop achieves low jitter by suppressing 1/f noise and does not require off-chip loop filter components. The operating range using a narrow-range VCO is from 10 to 200MHz. The output jitter over this range is <0.028UIpp. The chip is implemented in a 0.18mum CMOS process and consumes 50mW from a 1.8V supply