Y. Kanno, H. Mizuno, Y. Yasu, K. Hirose, Y. Shimazaki, T. Hoshi, Y. Miyairi, T. lshii, T. Yamada, T. Irita, T. Hattori, K. Yanagisawa, N. lrie
{"title":"Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor","authors":"Y. Kanno, H. Mizuno, Y. Yasu, K. Hirose, Y. Shimazaki, T. Hoshi, Y. Miyairi, T. lshii, T. Yamada, T. Irita, T. Hattori, K. Yanagisawa, N. lrie","doi":"10.1109/ICICDT.2007.4299537","DOIUrl":"https://doi.org/10.1109/ICICDT.2007.4299537","url":null,"abstract":"Hierarchical power distribution using a power tree is developed. It supports fine-grained power gating with dozens of power domains like fine-grained clock gating and effectively reduces leakage currents for 1-million-gate power domains to 1/4000 in multi-CPU processors with minimal area overhead. This paper demonstrates the integration of 20 power domains in a 90nm single-chip 3G cellular phone processor","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132417042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low power multimedia","authors":"Yiwan Wong, W. Namgoong","doi":"10.1109/isscc.2006.1696211","DOIUrl":"https://doi.org/10.1109/isscc.2006.1696211","url":null,"abstract":"","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126221386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Weinstein, Hengky Chandrahalim, L. F. Cheow, S. Bhave
{"title":"Dielectrically Transduced Single-Ended to Differential MEMS Filter","authors":"D. Weinstein, Hengky Chandrahalim, L. F. Cheow, S. Bhave","doi":"10.1109/ISSCC.2006.1696170","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696170","url":null,"abstract":"A single-ended input to balanced output 425MHz mechanically coupled electromechanical filter is presented. This technology provides 1MHz channel select filtering while eliminating the need for RF switches and baluns in front-end transceivers. The filter achieves 8dB insertion loss with -50dB stop-band rejection and -48dB common-mode suppression","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"10 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123520467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Nathawad, David J Weber, S. Abdollahi-Alibeik, Phoebe Chen, S. Enam, B. Kaczynski, A. Kheirkhahi, MeeLan Lee, S. Limotyrakis, K. Onodera, K. Vleugels, M. Zargari, B. Wooley
{"title":"An IEEE 802.11a/b/g SoC for Embedded WLAN Applications","authors":"L. Nathawad, David J Weber, S. Abdollahi-Alibeik, Phoebe Chen, S. Enam, B. Kaczynski, A. Kheirkhahi, MeeLan Lee, S. Limotyrakis, K. Onodera, K. Vleugels, M. Zargari, B. Wooley","doi":"10.1109/ISSCC.2006.1696193","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696193","url":null,"abstract":"An 802.11 a/b/g wireless LAN SoC for low-power embedded applications is implemented in a 0.18mum CMOS technology. The IC integrates the RF transceiver, digital PHY and MAC, CPU and host interface. For 64QAM OFDM, the 5GHz/2.4GHz TX EVM is -27.4dB/-27.5dB at an output power of -5.2dBm/-3.5dBm. Overall 5GHz/2.4GHz RX sensitivity is -73dBm/-76dBm at 54Mb/s","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115228177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ido, S. Ishizuka, Lars Risbo, Fumitaka Aoyagi, Toshi Hamasaki
{"title":"A Digital Input Controller for Audio Class-D Amplifiers with 100W 0.004% THD+N and 113dB DR","authors":"T. Ido, S. Ishizuka, Lars Risbo, Fumitaka Aoyagi, Toshi Hamasaki","doi":"10.1109/ISSCC.2006.1696185","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696185","url":null,"abstract":"A digital input controller for audio class-D amplifiers is presented. The controller utilizes specially configured integrated DAC and power stage feedback loop to suppress distortion components coming from power-stage switching with digital input capability. The class-D amplifier system with the controller and an existing power stage achieves 113dB DR, 0.0018% THD+N with 10W output power, and 0.004% THD+N with 100W output power into 4Omega load","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124402879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling","authors":"K. Nose, M. Kajita, M. Mizuno","doi":"10.1109/ISSCC.2006.1696271","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696271","url":null,"abstract":"An in-field real-time successive jitter-measurement macro is developed. It features interpolated jitter oversampling and feedforward calibration that help attain 1ps resolution and a hierarchical Vernier jitter-measurement technique that exploits the trade-off between rms and deterministic jitter measurement characteristics","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124403483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 0.36W 6b up to 20GS/s DAC for UWB Wave Formation","authors":"D. Baranauskas, D. Zelenin","doi":"10.1109/ISSCC.2006.1696301","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696301","url":null,"abstract":"A 6b up to 20GS/s DAC is presented. The DAC is used for direct synthesis of modulated waveforms for UWB communication. The DAC has a current-steering architecture for achieving 20GS/s, a 1.8V power supply, a 4:1 MUX for reducing the line data rate, and BIST. Fabricated in a SiGe process, it consumes 0.36W and has a FOM of 0.28pJ","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114668660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Toward Future Computer Entertainment Systems","authors":"K. Kutaragi","doi":"10.1109/ISSCC.2006.1696032","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696032","url":null,"abstract":"There are two elements in real-timeliness that a human being can intuitively sense. One is the continuity of motion that a human being can cognitively feel to be natural, and the other is response time between action and reaction. Correspondingly, of the applications that have advanced the concept of real-time computing is computer entertainment systems which originally started as computer games. Real-timeliness of computer entertainment systems must be quick enough to match the speed of the response time of the player. Lack of both processing power and data-transfer rate in achieving this level of real-timeliness using general-purpose microprocessors have motivated the development of a new breed of more-powerful processors built on a new architecture. In computer entertainment systems, since the hardware is normally fixed for several years, once its specifications are determined, there is an inclination to seek the most-advanced technology within the future roadmap, typically that of three years ahead, and one generation ahead in the semiconductor-fabrication process. As a consequence, a system must start off by utilizing large-size chipsets at launch, but, during its life cycle, it goes through two generations of semiconductor fabrication processes for downsizing, as well as progressive integration of chips to reduce manufacturing costs, and to enable mass production. Today, more than 40 million computer entertainment systems are shipped in a year, and are becoming a strong leading power in spearheading advancement in semiconductor technology and in creating demand. In the future of real-time computing, massive assembly of \"Parallel computing over the network\" to execute vast amounts of computation, and \"Vision System\" that recognize the real world, in real-time, from a vast number of sensors over the network, will lead the next era in real-time computing","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117212192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Free-Running Ring Frequency Synthesizer","authors":"D. Allen, A. L. Carley","doi":"10.1109/ISSCC.2006.1696201","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696201","url":null,"abstract":"A digital processor uses a single free-running ring oscillator to synthesize multiple clocks without analog circuits or feedback loops. Fabricated in 0.18mum technology, the 4mm2 die integrates 6 independent spread-spectrum synthesizers with <0.1ps period resolution. The synthesizers operate from 3 to 400MHz with a jitter <85ps, meeting PCIe clock-jitter requirements","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117261966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Floyd, S. Reynolds, U. Pfeiffer, T. Beukema, J. Grzyb, C. Haymes
{"title":"A silicon 60GHz receiver and transmitter chipset for broadband communications","authors":"B. Floyd, S. Reynolds, U. Pfeiffer, T. Beukema, J. Grzyb, C. Haymes","doi":"10.1109/ISSCC.2006.1696103","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696103","url":null,"abstract":"An integrated SiGe superheterodyne RX/TX pair capable of Gb/s data rates in the 60GHz band is described. The 6dB NF RX includes an image-reject LNA, a multistage down-converter with on-chip IF filters, a frequency tripler, a PLL, and baseband outputs. The 10 to 12dBm P1dBTX achieves 10% PAE in the final stage. It includes a PA, image-reject driver, multistage up-converter with on-chip filters, tripler, and PLL","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127090657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}