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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers最新文献

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A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface 一个0.03mm/sup 2/ 9mW宽范围占空比校正无假锁DLL与DDR接口的完全平衡电荷泵
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696176
Y. Tokunaga, S. Sakiyama, S. Dosho, Y. Doi, M. Hattori
{"title":"A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface","authors":"Y. Tokunaga, S. Sakiyama, S. Dosho, Y. Doi, M. Hattori","doi":"10.1109/ISSCC.2006.1696176","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696176","url":null,"abstract":"A duty-cycle-correcting false-lock-free DLL for DDR interface is proposed. A fully balanced charge-pump equalizes the charge and discharge pulses of the phase detector to reduce update noise. The DLL achieved 49% to 51% duty-cycle output from a 30% to 70% duty-cycle input clock operating from 20 to 300MHz, consumes 9mW from a 2 to 4V supply, and occupies 0.03mm2 in a 0.30mum CMOS process","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121727638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2V Organic Complementary Inverter 2V有机互补逆变器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696152
S. De Vusser, S. Steudel, K. Myny, Jan Genoe, P. Heremans
{"title":"A 2V Organic Complementary Inverter","authors":"S. De Vusser, S. Steudel, K. Myny, Jan Genoe, P. Heremans","doi":"10.1109/ISSCC.2006.1696152","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696152","url":null,"abstract":"A complementary organic thin-film transistor technology uses pentacene and F16CuPc as the p-type and n-type materials, respectively. The semiconductors are patterned by vacuum deposition through an integrated shadow mask, while tilting the substrate. Organic complementary inverters are realized that display an almost ideal inverter curve at a supply voltage of 2V, showing a gain of 14 and a noise margin of 0.65V","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123815242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 240ps 64b carry-lookahead adder in 90nm CMOS 90nm CMOS 240ps 64b超前进位加法器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696230
S. Kao, R. Zlatanovici, B. Nikolić
{"title":"A 240ps 64b carry-lookahead adder in 90nm CMOS","authors":"S. Kao, R. Zlatanovici, B. Nikolić","doi":"10.1109/ISSCC.2006.1696230","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696230","url":null,"abstract":"A 64b adder with a single-execution cycle time of 250ps is fabricated in a 90nm CMOS technology. The adder is designed using an energy-delay optimization framework that can rapidly optimize different microarchitectures in the energy-delay space. The microarchitecture with the lowest delay, a sparse radix-4 Ling parallel prefix tree, is chosen. The carry tree uses footless domino logic to minimize delay while the non-critical paths use minimum-size static logic to reduce energy. The adder consumes 311mW from a 1V supply","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131468391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters 用于偏置集成DC-DC变换器的快速数字控制线性稳压器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696279
P. Hazucha, S. T. Moon, G. Schrom, F. Paillet, Donald S. Gardner, S. Rajapandian, T. Karnik
{"title":"A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters","authors":"P. Hazucha, S. T. Moon, G. Schrom, F. Paillet, Donald S. Gardner, S. Rajapandian, T. Karnik","doi":"10.1109/ISSCC.2006.1696279","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696279","url":null,"abstract":"A high-voltage-tolerant 2.4 to 1.2V push-pull linear regulator with 1A output, 288ps response time, and 97.5% current efficiency for biasing integrated DC-to-DC converters is introduced. The regulator occupies 0.03mm2 in 90nm CMOS and achieves 33A/mm2 current density. Digital control with a flash ADC and a digital-to-current converter improve speed-power performance by 3times","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131936347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 250/spl mu/W 0.042mm2 2MS/s 9b DAC for Liquid Crystal Display Drivers 用于液晶显示驱动器的250/spl mu/W 0.042mm2 2MS/s 9b DAC
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696097
I. Knausz, R. Bowman
{"title":"A 250/spl mu/W 0.042mm2 2MS/s 9b DAC for Liquid Crystal Display Drivers","authors":"I. Knausz, R. Bowman","doi":"10.1109/ISSCC.2006.1696097","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696097","url":null,"abstract":"The architecture and design methods are presented for implementing N-bit DACs optimized for small-format LCD column drivers. Individual 9b DACs in a 12-channel QVGA display system occupies a die area of 0.042mm 2. It represents a composite DAC performance of better than 0.60pJ/b/mm2","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"26 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116628008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit 新一代SRAM写余量的重新定义及写余量监控电路
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696326
K. Takeda, H. Ikeda, Y. Hagihara, M. Nomura, H. Kobatake
{"title":"Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit","authors":"K. Takeda, H. Ikeda, Y. Hagihara, M. Nomura, H. Kobatake","doi":"10.1109/ISSCC.2006.1696326","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696326","url":null,"abstract":"We redefine write margin in order to be able to quantify the effect of both PVT variation and write-margin improvement. A write-margin monitoring circuit based on this definition is implemented in a 90nm CMOS process. This circuit can be applied to an SRAM power supply circuit to improve the write margin","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122283009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 94
A 360-Channel Speech Preprocessor that Emulates the Cochlear Amplifier 一种模拟耳蜗放大器的360声道语音预处理器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696289
Bo Wen, K. Boahen
{"title":"A 360-Channel Speech Preprocessor that Emulates the Cochlear Amplifier","authors":"Bo Wen, K. Boahen","doi":"10.1109/ISSCC.2006.1696289","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696289","url":null,"abstract":"A cochlea-based preprocessor for speech recognition emulates the fluid ducts with two 4680-element diffusive grids, the basilar membrane with 360 2nd-order sections, and the auditory nerve with 2160 pulse-frequency modulators. Integrated in 10.9mm2in 0.25mum CMOS and consuming 52mW, this silicon cochlea employs active bidirectional coupling, a selective amplification mechanism that sharpens tuning (Q10 is 2.7) and controls gain (24dB compression)","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131228927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
A chip-scale electrical soliton modelocked oscillator 芯片级电孤子模型锁定振荡器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696227
D. Ricketts, D. Ham
{"title":"A chip-scale electrical soliton modelocked oscillator","authors":"D. Ricketts, D. Ham","doi":"10.1109/ISSCC.2006.1696227","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696227","url":null,"abstract":"This paper introduces a chip-scale electrical soliton modelocked oscillator, which self-generates a periodic train of electrical soliton pulses. This circuit is made possible by combining a nonlinear transmission line (NLTL) with a unique amplifier that tames the instability-prone soliton dynamics in a closed-loop NLTL. This chip-scale prototype produces a pulse width of 293ps and demonstrates the feasibility for future widths close to 1ps, adding a new direction in pulse-based electronics","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134206015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor 用于POWER6处理器的4GHz+低延迟定点和二进制浮点执行单元
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696229
B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. Chan, D. Webber, Vaden Vaden, A. Goyal
{"title":"4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor","authors":"B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. Chan, D. Webber, Vaden Vaden, A. Goyal","doi":"10.1109/ISSCC.2006.1696229","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696229","url":null,"abstract":"A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133180166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A Programmable MEMS FSK Transmitter 一个可编程的MEMS FSK发射机
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696156
W. Hsu, Andrew R. Brown, K. Cioffi
{"title":"A Programmable MEMS FSK Transmitter","authors":"W. Hsu, Andrew R. Brown, K. Cioffi","doi":"10.1109/ISSCC.2006.1696156","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696156","url":null,"abstract":"An FSK transmitter is modulated by changing the polarization voltage of a micromechanical resonator. The transmitter frequency can be programmed from 2 to 437MHz with 1ppm accuracy. The transmitter has 6times greater frequency deviation than quartz-based FSK modulators, 20kb/s data rate, and total 8ppm frequency variation from -40 to 85degC","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132028598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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