一个0.03mm/sup 2/ 9mW宽范围占空比校正无假锁DLL与DDR接口的完全平衡电荷泵

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696176

Y. Tokunaga, S. Sakiyama, S. Dosho, Y. Doi, M. Hattori

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引用次数: 5

摘要

提出了一种用于DDR接口的空占比校正无假锁DLL。一个完全平衡的电荷泵平衡了鉴相器的充放电脉冲，以降低更新噪声。该DLL在20 ~ 300MHz范围内工作，从30% ~ 70%的占空比输入时钟实现49% ~ 51%的占空比输出，从2 ~ 4V电源消耗9mW，在0.30mum CMOS工艺中占用0.03mm2

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A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface

A duty-cycle-correcting false-lock-free DLL for DDR interface is proposed. A fully balanced charge-pump equalizes the charge and discharge pulses of the phase detector to reduce update noise. The DLL achieved 49% to 51% duty-cycle output from a 30% to 70% duty-cycle input clock operating from 20 to 300MHz, consumes 9mW from a 2 to 4V supply, and occupies 0.03mm2 in a 0.30mum CMOS process

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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