4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696229

B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. Chan, D. Webber, Vaden Vaden, A. Goyal

引用次数: 20

Abstract

A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases

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用于POWER6处理器的4GHz+低延迟定点和二进制浮点执行单元

1管道级，低延迟，13 FO4, 64b定点执行单元，在65nm SOI CMOS工艺中实现，允许背靠背执行数据相关的加法，减法，比较，移位，旋转和逻辑操作。在大多数情况下，一个7管道级，91 FO4，双精度浮点单元允许在6个周期后转发相关结果

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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