{"title":"用于液晶显示驱动器的250/spl mu/W 0.042mm2 2MS/s 9b DAC","authors":"I. Knausz, R. Bowman","doi":"10.1109/ISSCC.2006.1696097","DOIUrl":null,"url":null,"abstract":"The architecture and design methods are presented for implementing N-bit DACs optimized for small-format LCD column drivers. Individual 9b DACs in a 12-channel QVGA display system occupies a die area of 0.042mm 2. It represents a composite DAC performance of better than 0.60pJ/b/mm2","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"26 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 250/spl mu/W 0.042mm2 2MS/s 9b DAC for Liquid Crystal Display Drivers\",\"authors\":\"I. Knausz, R. Bowman\",\"doi\":\"10.1109/ISSCC.2006.1696097\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The architecture and design methods are presented for implementing N-bit DACs optimized for small-format LCD column drivers. Individual 9b DACs in a 12-channel QVGA display system occupies a die area of 0.042mm 2. It represents a composite DAC performance of better than 0.60pJ/b/mm2\",\"PeriodicalId\":166617,\"journal\":{\"name\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"volume\":\"26 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2006.1696097\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2006.1696097","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 250/spl mu/W 0.042mm2 2MS/s 9b DAC for Liquid Crystal Display Drivers
The architecture and design methods are presented for implementing N-bit DACs optimized for small-format LCD column drivers. Individual 9b DACs in a 12-channel QVGA display system occupies a die area of 0.042mm 2. It represents a composite DAC performance of better than 0.60pJ/b/mm2