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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers最新文献

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A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration 基于lms的DAC增益校准的1.8GHz杂散抵消分数n频率合成器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696250
M. Gupta, B. Song
{"title":"A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration","authors":"M. Gupta, B. Song","doi":"10.1109/ISSCC.2006.1696250","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696250","url":null,"abstract":"A 1.8GHz wideband fractional-N synthesizer achieves the phase noise of an integer-N PLL using a noise-cancellation DAC calibrated with an adaptive LMS spur correlation technique. It exhibits in-band and integrated phase noises of -98dBc/Hz and 0.8deg, respectively. The chip in 0.18mum CMOS occupies 2mm2, and consumes 29mW at 1.8V","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116223280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS 90nm CMOS的800MHz至5GHz软件定义无线电接收机
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696251
R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, Minjae Lee, M. Mikhemar, Wai K. Tang, A. Abidi
{"title":"An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS","authors":"R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, Minjae Lee, M. Mikhemar, Wai K. Tang, A. Abidi","doi":"10.1109/ISSCC.2006.1696251","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696251","url":null,"abstract":"A 90nm CMOS RX operates over the 800MHz to 5GHz band uses a passive FET mixer driven by a capacitively coupled RF transconductor, and a combination of CT and DT analog FIR and MR filters to achieve >100dB of programmable anti-aliasing. The RX chain has 5 to 5.5dB NF, -3.5dBm IIP3, 39dBm IIP2, 10 to 66dB of gain, and draws 11.4mA from 2.5V and 8 to 28mA (depending on RX mode) from 1V","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125403250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 126
A 1.1ghz charge-recovery logic 1.1ghz电荷恢复逻辑
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696205
V. Sathe, Juang-Ying Chueh, Marios Papaefthymio
{"title":"A 1.1ghz charge-recovery logic","authors":"V. Sathe, Juang-Ying Chueh, Marios Papaefthymio","doi":"10.1109/ISSCC.2006.1696205","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696205","url":null,"abstract":"A GHz-class dynamic charge-recovery logic is implemented with an on-chip clock generator and integrated inductor in a 0.13mum CMOS process. The chip operation is verified at clock frequencies up to 1.3GHz. At its natural frequency, the design recovers 60% of total circuit energy every cycle","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126644566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 3.4Mb/s RFID Front-end for Proximity Applications Based on a Delta-modulator 基于增量调制器的3.4Mb/s射频识别前端
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696167
B. Gomez, G. Masson, P. Villard, G. Robert, F. Dehmas, Jacques Reverdy
{"title":"A 3.4Mb/s RFID Front-end for Proximity Applications Based on a Delta-modulator","authors":"B. Gomez, G. Masson, P. Villard, G. Robert, F. Dehmas, Jacques Reverdy","doi":"10.1109/ISSCC.2006.1696167","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696167","url":null,"abstract":"A 13.56MHz RFID front-end uses multi-level signaling to achieve 3.4Mb/s operation. The circuit is built around a delta-modulator loop which ensures demodulation and ADC functions as well as supply-voltage regulation. The circuits are fabricated in a 6M 0.18mum 1.8V digital CMOS process in an area of <0.5mm2","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127077874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An integrated VCSEL driver for 10Gb ethernet in 0.13/spl mu/m CMOS 一个集成的VCSEL驱动程序为10Gb以太网在0.13/spl mu/m CMOS
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696134
S. Rabii, Nikhil Acharya, P. Chau, J. Dao, A. Feldman, H. Liaw, Dean Liu, M. Loinaz, Manuel Luschas, A. Salleh, Siddharth Sheth, S. Sidiropoulos, D. Stark, S. Verma
{"title":"An integrated VCSEL driver for 10Gb ethernet in 0.13/spl mu/m CMOS","authors":"S. Rabii, Nikhil Acharya, P. Chau, J. Dao, A. Feldman, H. Liaw, Dean Liu, M. Loinaz, Manuel Luschas, A. Salleh, Siddharth Sheth, S. Sidiropoulos, D. Stark, S. Verma","doi":"10.1109/ISSCC.2006.1696134","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696134","url":null,"abstract":"A 10.3Gb/s VCSEL driver is integrated with a complete Ethernet transceiver in a standard 0.13mum CMOS process. When driving a VCSEL differentially, the resulting optical eye exceeds the 10Gb/s Ethernet mask by 35%. Intended for short-reach applications, the driver dissipates 85mW from 1.2V and occupies 0.15mm2","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125844383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 2.2GHz sub-harmonic mixer for directconversion receivers in 0.13/spl mu/m CMOS 用于0.13/spl mu/m CMOS直接转换接收器的2.2GHz次谐波混频器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696241
Henry C. Jen, S. Rose, R. Meyer
{"title":"A 2.2GHz sub-harmonic mixer for directconversion receivers in 0.13/spl mu/m CMOS","authors":"Henry C. Jen, S. Rose, R. Meyer","doi":"10.1109/ISSCC.2006.1696241","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696241","url":null,"abstract":"A 0.13mum CMOS sub-harmonic mixer uses a passive switching network to achieve a dc offset of 0.7mV and a 2timesLO leakage of -91dBm at the RF port. The LO leakage is -95dBm, and the flicker-noise corner is 100kHz. The mixer requires an LO input power of -18dBm and consumes 13mW from a 1.2V supply","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126167526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Neurons to Silicon: Implantable Prosthesis Processor 神经元到硅:植入式假体处理器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696287
S. O'Driscoll, T. Meng, K. Shenoy, C. Kemere
{"title":"Neurons to Silicon: Implantable Prosthesis Processor","authors":"S. O'Driscoll, T. Meng, K. Shenoy, C. Kemere","doi":"10.1109/ISSCC.2006.1696287","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696287","url":null,"abstract":"A processor architecture for neural prosthesis control is described. It implements real-time neural decoding from a permanently implanted electrode array to reduce the data rate from 80Mb/s to 20b/s, minimizing the wireless communication requirements. The neural signals are digitized by a 100-channel 100kS/s adaptive-resolution ADC array consuming 1muW per channel","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122028516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A 1.8dB NF 112mW Single-Chip Diversity Tuner for 2.6GHz S-DMB Applications 用于2.6GHz S-DMB应用的1.8dB NF 112mW单芯片分集调谐器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696319
Myung-Woon Hwan, Sungho Beck, Sunki Min, Sang-Hoon Lee, S. Yoo, Kyoohyun Lim, H. Jung, Jeong-Cheol Lee, Seokyong Hong, Changhee Lee, Kyung-Lok Kim, Hyunji Song, G. Cho, Sangwoo Han
{"title":"A 1.8dB NF 112mW Single-Chip Diversity Tuner for 2.6GHz S-DMB Applications","authors":"Myung-Woon Hwan, Sungho Beck, Sunki Min, Sang-Hoon Lee, S. Yoo, Kyoohyun Lim, H. Jung, Jeong-Cheol Lee, Seokyong Hong, Changhee Lee, Kyung-Lok Kim, Hyunji Song, G. Cho, Sangwoo Han","doi":"10.1109/ISSCC.2006.1696319","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696319","url":null,"abstract":"The fully-monolithic diversity 2.6GHz S-DMB tuner IC features a NF of <1.8dB, a path isolation of over 25dB, a DR of over 100dB with <4dB path gain mismatch and a power consumption of 112mW. This IC is implemented in a 0.25 mum SiGe BiCMOS process. The chip is verified in S-DMB systems using several commercially available S-DMB demodulator chips","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126348147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Current Driver IC using a S/H for QVGA FullColor Active-Matrix Organic LED Mobile Displays 用于QVGA全彩有源矩阵有机LED移动显示器的S/H电流驱动IC
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696098
J. Baek, Jaehoon Lee, Hansu Pae, Chang-Ju Lee, Jongseon Kim, Myunghee Lee, Jintae Kim, C. Choi, H. Kim, Tae Jin Kim, H. Chung
{"title":"A Current Driver IC using a S/H for QVGA FullColor Active-Matrix Organic LED Mobile Displays","authors":"J. Baek, Jaehoon Lee, Hansu Pae, Chang-Ju Lee, Jongseon Kim, Myunghee Lee, Jintae Kim, C. Choi, H. Kim, Tae Jin Kim, H. Chung","doi":"10.1109/ISSCC.2006.1696098","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696098","url":null,"abstract":"A current driver with 720 outputs for active-matrix organic LEDs uses a current-copier scheme to produce 64 gray levels with maximum 2% error from 10nA to 10uA on a 19.2 times 17.8mm2 die","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124296614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Panel-Sized TFT-LCD Column Driver 面板大小的TFT-LCD列驱动器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696099
O. Ishibashi, M. Iriguchi, Keigo Kimura, J. Ishii, D. Sasaki, Hideyuki Imai, H. Tsuchi, H. Hayama
{"title":"Panel-Sized TFT-LCD Column Driver","authors":"O. Ishibashi, M. Iriguchi, Keigo Kimura, J. Ishii, D. Sasaki, Hideyuki Imai, H. Tsuchi, H. Hayama","doi":"10.1109/ISSCC.2006.1696099","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696099","url":null,"abstract":"Panel-sized TFT-LCD column drivers have been fabricated on a glass substrate with TF CMOS and low-resistivity copper-plated interconnections. These operate with a 16.25MHz internal clock, have 6b DACs, 6b accuracy with either 3072 or 1536 outputs, and use an offset-controlled amplifier. The operation of 15 inch XGA LCDs is demonstrated using panel-sized column drivers.","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121894623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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