神经元到硅:植入式假体处理器

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696287

S. O'Driscoll, T. Meng, K. Shenoy, C. Kemere

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引用次数: 33

摘要

介绍了一种神经假体控制的处理器结构。它通过永久植入的电极阵列实现实时神经解码，将数据速率从80Mb/s降低到20b/s，最大限度地降低了无线通信要求。神经信号由100通道100kS/s自适应分辨率ADC阵列数字化，每通道消耗1muW

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Neurons to Silicon: Implantable Prosthesis Processor

A processor architecture for neural prosthesis control is described. It implements real-time neural decoding from a permanently implanted electrode array to reduce the data rate from 80Mb/s to 20b/s, minimizing the wireless communication requirements. The neural signals are digitized by a 100-channel 100kS/s adaptive-resolution ADC array consuming 1muW per channel

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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