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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers最新文献

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A 4b/cell NROM 1Gb Data-Storage Memory 一个4b/cell NROM 1Gb数据存储内存
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696077
Y. Polansky, A. Lavan, R. Sahar, O. Dadashev, Y. Betser, G. Cohen, E. Maayan, B. Eitan, F. Ni, Y. Ku, Chih-Yuan Lu, T. Chen, Chun-Yu Liao, Chin-Hung Chang, C. Chen, Wen-Chiao Ho, Y. Shih, W. Ting, Wenpin Lu
{"title":"A 4b/cell NROM 1Gb Data-Storage Memory","authors":"Y. Polansky, A. Lavan, R. Sahar, O. Dadashev, Y. Betser, G. Cohen, E. Maayan, B. Eitan, F. Ni, Y. Ku, Chih-Yuan Lu, T. Chen, Chun-Yu Liao, Chin-Hung Chang, C. Chen, Wen-Chiao Ho, Y. Shih, W. Ting, Wenpin Lu","doi":"10.1109/ISSCC.2006.1696077","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696077","url":null,"abstract":"A 4b/cell 1Gb data flash based on a low-cost NROM process technology is achieved. The design includes a two-phase programming algorithm for supporting a fast and accurate threshold-voltage control. The read scheme incorporates a simple error-detection mechanism combined with an accurate drain-side sensing circuit with a built-in offset cancellation","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133421182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory 124Ms/s像素流水线运动- jpeg 2000编解码器，不带内存
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696213
Yu-Wei Chang, Hung-Chi Fang, Chih-Chi Cheng, Chun-Chia Chen, Chung-Jr Lian, Shao-Yi Chien, Liang-Gee Chen
{"title":"124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory","authors":"Yu-Wei Chang, Hung-Chi Fang, Chih-Chi Cheng, Chun-Chia Chen, Chung-Jr Lian, Shao-Yi Chien, Liang-Gee Chen","doi":"10.1109/ISSCC.2006.1696213","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696213","url":null,"abstract":"A JPEG2000 codec capable of processing 1920times1080 HD video at 30frames/s is implemented on a 20.1mm2 die with 0.18mum CMOS technology dissipating 345mW at 1.8V and 42MHz. The level-switched schedule eliminates the 192kB tile memory. Hardware sharing between encoder and decoder reduces silicon area by 40%","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127814590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction 采用动态列FPN降阶的CMOS列级ADC成像仪
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696260
Martijn F. Snoeij, A. Theuwissen, K. Makinwa, J. Huijsing
{"title":"A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction","authors":"Martijn F. Snoeij, A. Theuwissen, K. Makinwa, J. Huijsing","doi":"10.1109/ISSCC.2006.1696260","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696260","url":null,"abstract":"A CMOS imager with a column-level ADC uses a dynamic column FPN reduction technique. This technique requires 5 extra switches per column and minimal digital overhead at the chip level while reducing the perceptual effect of column FPN. Measurements show that the prototype makes a column FPN of plusmn0.67% nearly invisible","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121412874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching 具有完全分段动态元件匹配的14b 100MS/s DAC
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696302
Kok Lim Chan, I. Galton
{"title":"A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching","authors":"Kok Lim Chan, I. Galton","doi":"10.1109/ISSCC.2006.1696302","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696302","url":null,"abstract":"A 14b 100MS/s Nyquist-rate DAC using a segmented dynamic-element-matching technique involving all the DAC elements is demonstrated. The DAC is implemented in a 0.18mum CMOS process and worst-case SFDRs across Nyquist bands are 74.4dB and 78.9dB for sample-rates of 100MS/s and 70Ms/s, respectively","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121433788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
A 2.5Gb/s Multi-Rate 0.25/spl mu/m CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter 利用混合模拟/数字环路滤波器的2.5Gb/s多速率0.25/spl mu/m CMOS CDR
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696175
M. Perrott, Yunteng Huang, R. Baird, B. Garlepp, Ligang Zhang, J. Hein
{"title":"A 2.5Gb/s Multi-Rate 0.25/spl mu/m CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter","authors":"M. Perrott, Yunteng Huang, R. Baird, B. Garlepp, Ligang Zhang, J. Hein","doi":"10.1109/ISSCC.2006.1696175","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696175","url":null,"abstract":"A CDR comprises a Hogge detector and a 1st-order DeltaSigmaADC, and uses a hybrid analog/digital loop filter to enhance integration and allow bandwidth tuning over a wide range of data rates from 155Mb/s to 2.7Gb/s. The CDR exceeds SONET performance at relevant data rates and generates 1.2psrms jitter at 2.5Gb/s","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128560676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics 基于硅纳米光子学的高速VLSI芯片的光互连技术
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696224
K. Ohashi, J. Fujikata, M. Nakada, T. Ishi, K. Nishi, H. Yamada, M. Fukaishi, M. Mizuno, K. Nose, I. Ogura, Y. Urino, T. Baba
{"title":"Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics","authors":"K. Ohashi, J. Fujikata, M. Nakada, T. Ishi, K. Nishi, H. Yamada, M. Fukaishi, M. Mizuno, K. Nose, I. Ogura, Y. Urino, T. Baba","doi":"10.1109/ISSCC.2006.1696224","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696224","url":null,"abstract":"Optoelectronic and electrooptic elements are integrated on VLSI chips. The junction capacitance of a nano-photodiode is extremely low (<10aF), which permits a high load resistance to be used, resulting in higher output voltage at high frequencies. A ceramic Pb(,ZrTi)O3 film with average crystallite diameter below 20nm has a high electro-optical coefficient (>150pm/V) suitable for on-chip modulators. This paper introduces a new approach for realizing high-speed optical interconnects on silicon chips. This concept uses nano-photodiodes on silicon with extremely low parasitic capacitance (less than 10aF) enabling robust communication at very high frequencies. The results demonstrate 5GHz clocking with the promise of up to 20GHz. The authors will also discuss how the silicon nano-photodiode can be used for wavelength-division multiplexing and low-voltage electro-optic modulators for on-chip and off-chip optical communications","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128746242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 77GHz 4-Element Phased Array Receiver with On-Chip Dipole Antennas in Silicon 采用硅片上偶极子天线的77GHz 4元相控阵接收机
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696101
A. Babakhani, Xiang Guan, A. Komijani, A. Natarajan, A. Hajimiri
{"title":"A 77GHz 4-Element Phased Array Receiver with On-Chip Dipole Antennas in Silicon","authors":"A. Babakhani, Xiang Guan, A. Komijani, A. Natarajan, A. Hajimiri","doi":"10.1109/ISSCC.2006.1696101","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696101","url":null,"abstract":"On-chip antennas are used in a fully integrated phased-array receiver at 77GHz. The complete down-conversion, power-combining, and phase-generation functions are integrated in silicon with no external mm-wave electrical connections. Each of the 4 receiver elements has 41dB of gain with a NF of 8dB with a system BW of 3GHz","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116716274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
A multipath technique for canceling harmonics and sidebands in a wideband power upconverter 在宽带功率上变频器中消除谐波和边带的多径技术
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696237
R. Shrestha, E. Mensink, E. Klumperink, G. Wienk, B. Nauta
{"title":"A multipath technique for canceling harmonics and sidebands in a wideband power upconverter","authors":"R. Shrestha, E. Mensink, E. Klumperink, G. Wienk, B. Nauta","doi":"10.1109/ISSCC.2006.1696237","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696237","url":null,"abstract":"Switching mixers are power-efficient but produce unwanted harmonics and sidebands. A multipath technique to clean up the spectrum using digital circuits and mixers, but no filters, is applied to a 0.13mum CMOS power upconverter. The circuit delivers 8mW from dc to 2.4GHz with 11% drain efficiency, with spurs <-40dBc over more than 4 octaves in frequency, and consumes 228mW from a 1.2V supply","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"888 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117059129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
An IP2 Improvement Technique for Zero-IF Down-Converters 零中频下变频器的IP2改进技术
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696243
H. Darabi, Hea Joung Kim, J. Chiu, B. Ibrahim, L. Serrano
{"title":"An IP2 Improvement Technique for Zero-IF Down-Converters","authors":"H. Darabi, Hea Joung Kim, J. Chiu, B. Ibrahim, L. Serrano","doi":"10.1109/ISSCC.2006.1696243","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696243","url":null,"abstract":"An IP2 calibration circuit to improve the 2nd-order nonlinearity of mixers in zero or low-IF receivers is presented. The circuit allows the mixers to be optimized independently, and has negligible impact on receiver noise figure, area, and power consumption. A prototype transceiver including the calibration circuitry in 0.13mum CMOS is fabricated. An average IIP2 improvement of 18dB is measured","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114517367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A single-chip linear CMOS power amplifier for 2.4 GHz WLAN 用于2.4 GHz WLAN的单片线性CMOS功率放大器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696115
Jongchan Kang, A. Hajimiri, Bumman Kim
{"title":"A single-chip linear CMOS power amplifier for 2.4 GHz WLAN","authors":"Jongchan Kang, A. Hajimiri, Bumman Kim","doi":"10.1109/ISSCC.2006.1696115","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696115","url":null,"abstract":"A single-chip linear CMOS PA for OFDM WLAN applications adopts a fully differential topology with transformer-type output matching and operates from a 3.3V supply. All of the components, including the input balun and output transformer, are integrated on a single 0.18mum CMOS die and no off-chip component is required","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115317745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
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