A 2.5Gb/s Multi-Rate 0.25/spl mu/m CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696175

M. Perrott, Yunteng Huang, R. Baird, B. Garlepp, Ligang Zhang, J. Hein

引用次数: 4

Abstract

A CDR comprises a Hogge detector and a 1st-order DeltaSigmaADC, and uses a hybrid analog/digital loop filter to enhance integration and allow bandwidth tuning over a wide range of data rates from 155Mb/s to 2.7Gb/s. The CDR exceeds SONET performance at relevant data rates and generates 1.2psrms jitter at 2.5Gb/s

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利用混合模拟/数字环路滤波器的2.5Gb/s多速率0.25/spl mu/m CMOS CDR

CDR包括Hogge检测器和一阶DeltaSigmaADC，并使用混合模拟/数字环路滤波器来增强集成，并允许在155Mb/s至2.7Gb/s的数据速率范围内进行带宽调整。话单在相关数据速率下超过SONET性能，在2.5Gb/s速率下产生1.2psrms的抖动

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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