A 4b/cell NROM 1Gb Data-Storage Memory

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696077

Y. Polansky, A. Lavan, R. Sahar, O. Dadashev, Y. Betser, G. Cohen, E. Maayan, B. Eitan, F. Ni, Y. Ku, Chih-Yuan Lu, T. Chen, Chun-Yu Liao, Chin-Hung Chang, C. Chen, Wen-Chiao Ho, Y. Shih, W. Ting, Wenpin Lu

引用次数: 9

Abstract

A 4b/cell 1Gb data flash based on a low-cost NROM process technology is achieved. The design includes a two-phase programming algorithm for supporting a fast and accurate threshold-voltage control. The read scheme incorporates a simple error-detection mechanism combined with an accurate drain-side sensing circuit with a built-in offset cancellation

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一个4b/cell NROM 1Gb数据存储内存

实现了基于低成本NROM工艺技术的4b/cell 1Gb数据闪存。该设计包括一个两阶段的编程算法，以支持快速和准确的阈值电压控制。读取方案结合了一个简单的错误检测机制，结合了一个精确的漏极侧传感电路，内置偏移抵消

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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