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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers最新文献

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Wideband Image-Rejection Circuit for Low-IF Receivers 用于低中频接收机的宽带图像抑制电路
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696249
K. Maeda, W. Hioe, Yasuyuki Kimura, S. Tanaka
{"title":"Wideband Image-Rejection Circuit for Low-IF Receivers","authors":"K. Maeda, W. Hioe, Yasuyuki Kimura, S. Tanaka","doi":"10.1109/ISSCC.2006.1696249","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696249","url":null,"abstract":"A wideband image-rejection circuit for GSM/EDGE low-IF receivers includes a reference signal source and digital correction circuit that compensate I/Q gain, phase, and frequency response mismatch. The chip integrates an LNA, mixers, PGAs, LPFs, and fractional-N synthesizer in a 0.25mum BiCMOS process and achieves 50dB IRR over the entire signal bandwidth at 200kHz IF","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116636020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A UMTS-complaint fully digitally controlled oscillator with 100Mhz fine-tuning range in 0.13/spl mu/m CMOS 在0.13/spl mu/m CMOS中具有100Mhz微调范围的umts -投诉全数字控制振荡器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696116
T. Pittorino, Y. Chen, V. Neubauer, T. Mayer, L. Maurer
{"title":"A UMTS-complaint fully digitally controlled oscillator with 100Mhz fine-tuning range in 0.13/spl mu/m CMOS","authors":"T. Pittorino, Y. Chen, V. Neubauer, T. Mayer, L. Maurer","doi":"10.1109/ISSCC.2006.1696116","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696116","url":null,"abstract":"A 0.13mum CMOS fully digitally controlled oscillator is presented. Running at 2GHz, it draws 3.2mA from a 2.5V supply and has a phase noise of -118dBc/Hz at 1MHz offset, as required for UMTS oscillators. A tuning range from 3.45 to 4.45GHz is achieved by using binary-weighted and thermometer-coded switchable capacitors, which allow a maximum frequency step of 200kHz","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117231159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13/spl mu/m CMOS 一种0.13/spl mu/m CMOS 10Gb/s突发模式自适应增益选择限制放大器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696135
M. Nogawa, Y. Ohtomo, S. Kimura, K. Nishimura, T. Kawamura, M. Togashi
{"title":"A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13/spl mu/m CMOS","authors":"M. Nogawa, Y. Ohtomo, S. Kimura, K. Nishimura, T. Kawamura, M. Togashi","doi":"10.1109/ISSCC.2006.1696135","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696135","url":null,"abstract":"A 10Gb/s burst-mode limiting amplifier is developed in a 0.13mum CMOS process. An adaptive gain-selection technique achieves a settling time of 0.8ns and a wide input dynamic range of 28dB, which is five-times wider than that of previous work at 10Gb/s","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131192843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications 一个120Mvertices/s的多线程VLIW顶点处理器，用于移动多媒体应用
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696215
Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, L. Kim
{"title":"A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications","authors":"Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, L. Kim","doi":"10.1109/ISSCC.2006.1696215","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696215","url":null,"abstract":"A 3D vertex processor with a floating-point 4-threaded and 4-issue VLIW architecture and a TnL vertex cache is implemented for mobile multimedia applications in a 0.18mum 4M CMOS process. The proposed architecture efficiently reduces the total energy consumption and achieves 120Mvertices/s with a 2.5GFLOPS datapath using 157mW when operating at 100MHz","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 65nm low-power embedded DRAM with extended data-retention sleep mode 具有扩展数据保留休眠模式的65nm低功耗嵌入式DRAM
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696093
T. Nagai, M. Wada, H. Iwai, Mariko Kaku, A. Suzuki, Tomohisa Takai, Naoko Itoga, T. Miyazaki, H. Takenaka, T. Hojo, S. Miyano
{"title":"A 65nm low-power embedded DRAM with extended data-retention sleep mode","authors":"T. Nagai, M. Wada, H. Iwai, Mariko Kaku, A. Suzuki, Tomohisa Takai, Naoko Itoga, T. Miyazaki, H. Takenaka, T. Hojo, S. Miyano","doi":"10.1109/ISSCC.2006.1696093","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696093","url":null,"abstract":"An extended data retention (EDR) sleep mode with ECC and MT-CMOS is proposed for embedded DRAM power reduction. In sleep mode, the retention time improves by 8 times and the leakage current is reduced to 13% of the normal operation mode. Since ECC scrubbing operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low-power embedded DRAM macro featuring 400MHz operation and 0.39mW of data-retention power is realized","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131865741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 60/spl mu/W 60 nV/Hz Readout Front-End for Portable Biopotential Acquisition Systems 一种用于便携式生物电位采集系统的60/spl mu/W 60 nV/Hz读出前端
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696039
R. Yazicioglu, P. Merken, R. Puers, C. Hoof
{"title":"A 60/spl mu/W 60 nV/Hz Readout Front-End for Portable Biopotential Acquisition Systems","authors":"R. Yazicioglu, P. Merken, R. Puers, C. Hoof","doi":"10.1109/ISSCC.2006.1696039","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696039","url":null,"abstract":"A biopotential readout front-end can be configured to extract EEG, ECG, and EMG signals and draws 20muA from 3V. AC coupling of chopped amplifiers results in an input-referred noise of 60nV/radicHz and CMRR of 120dB at 1kHz. The immunity of the CMRR to electrode offset voltages is improved with an active input stage and 110dB CMRR is achieved at 100Hz with 50mV electrode offset","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"20 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131892796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Minimally Invasive Retinal Prosthesis 微创视网膜假体
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696038
L. Theogarajan, J. Wyatt, J. Rizzo, Bill Drohan, M. Markova, S. Kelly, G. Swider, M. Raj, D. Shire, M. Gingerich, J. Lowenstein, B. Yomtov
{"title":"Minimally Invasive Retinal Prosthesis","authors":"L. Theogarajan, J. Wyatt, J. Rizzo, Bill Drohan, M. Markova, S. Kelly, G. Swider, M. Raj, D. Shire, M. Gingerich, J. Lowenstein, B. Yomtov","doi":"10.1109/ISSCC.2006.1696038","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696038","url":null,"abstract":"A wireless retinal implant with a low-power area-efficient stimulator chip features an ASK demodulator, single-ended-to-differential converter, low-power DLL and programmable current drivers. The chip dissipates 1.3mW from plusmn2.5V at a data rate of 100kb/s. The chip is powered and driven through a wireless inductive link separated by 15mm","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134395930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
Analog Signal Processing with Organic FETs 用有机场效应管处理模拟信号
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696150
N. Gay, Wolf-Joachim Fischer, M. Halik, H. Klauk, U. Zschieschang, Günter Schmid
{"title":"Analog Signal Processing with Organic FETs","authors":"N. Gay, Wolf-Joachim Fischer, M. Halik, H. Klauk, U. Zschieschang, Günter Schmid","doi":"10.1109/ISSCC.2006.1696150","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696150","url":null,"abstract":"Regular and differential amplifiers as well as differential-to-single-ended circuits based on organic FETs (OFETs) are demonstrated. A numerical OFET model suitable for analog design is developed. Unity-gain bandwidths in excess of 1.4kHz and DC-gains of 10dB are achieved","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134532503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS 一种采用65nm CMOS的10b 10GHz数控LC振荡器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696105
N. D. Dalt, C. Kropf, M. Burian, T. Hartig, H. Eul
{"title":"A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS","authors":"N. D. Dalt, C. Kropf, M. Burian, T. Hartig, H. Eul","doi":"10.1109/ISSCC.2006.1696105","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696105","url":null,"abstract":"A digitally controlled LC oscillator (DCO) is integrated in a digital 65nm CMOS technology. The frequency can be fine tuned with 10b from 9.87 to 10.92GHZ (10%) with a frequency step of 1.03MHz/LSB. The DCO draws 3.0mA from a 1.1V supply and achieves a phase noise of -102dBc/Hz at 1MHz offset (FOM=-177.2dBc/Hz)","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"555 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133384704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS 一种用于40GHz锁相环的80nm CMOS动态与静态组合分频器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696310
G. V. Büren, C. Kromer, F. Ellinger, A. Huber, M. Schmatz, H. Jäckel
{"title":"A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS","authors":"G. V. Büren, C. Kromer, F. Ellinger, A. Huber, M. Schmatz, H. Jäckel","doi":"10.1109/ISSCC.2006.1696310","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696310","url":null,"abstract":"A divide-by-4 circuit operates for input frequencies from 31 to 41 GHz at signal amplitudes \"0.5Vpp. The circuit consists of a dynamic followed by a static frequency divider. The dynamic and static frequency dividers consume 2mA and 1mA, respectively, from a 1.1V supply","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"367 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133304773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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