A 65nm low-power embedded DRAM with extended data-retention sleep mode

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696093

T. Nagai, M. Wada, H. Iwai, Mariko Kaku, A. Suzuki, Tomohisa Takai, Naoko Itoga, T. Miyazaki, H. Takenaka, T. Hojo, S. Miyano

引用次数: 19

Abstract

An extended data retention (EDR) sleep mode with ECC and MT-CMOS is proposed for embedded DRAM power reduction. In sleep mode, the retention time improves by 8 times and the leakage current is reduced to 13% of the normal operation mode. Since ECC scrubbing operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low-power embedded DRAM macro featuring 400MHz operation and 0.39mW of data-retention power is realized

查看原文本刊更多论文

具有扩展数据保留休眠模式的65nm低功耗嵌入式DRAM

提出了一种基于ECC和MT-CMOS的扩展数据保留(EDR)睡眠模式，用于降低嵌入式DRAM功耗。在休眠模式下，保持时间提高了8倍，漏电流降低到正常工作模式的13%。由于ECC刷洗仅在EDR休眠模式下操作，因此读写性能不会降低。实现了一个工作频率为400MHz、数据保留功率为0.39mW的65nm低功耗嵌入式DRAM宏

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

自引率

0.00%

发文量