{"title":"用于低中频接收机的宽带图像抑制电路","authors":"K. Maeda, W. Hioe, Yasuyuki Kimura, S. Tanaka","doi":"10.1109/ISSCC.2006.1696249","DOIUrl":null,"url":null,"abstract":"A wideband image-rejection circuit for GSM/EDGE low-IF receivers includes a reference signal source and digital correction circuit that compensate I/Q gain, phase, and frequency response mismatch. The chip integrates an LNA, mixers, PGAs, LPFs, and fractional-N synthesizer in a 0.25mum BiCMOS process and achieves 50dB IRR over the entire signal bandwidth at 200kHz IF","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Wideband Image-Rejection Circuit for Low-IF Receivers\",\"authors\":\"K. Maeda, W. Hioe, Yasuyuki Kimura, S. Tanaka\",\"doi\":\"10.1109/ISSCC.2006.1696249\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A wideband image-rejection circuit for GSM/EDGE low-IF receivers includes a reference signal source and digital correction circuit that compensate I/Q gain, phase, and frequency response mismatch. The chip integrates an LNA, mixers, PGAs, LPFs, and fractional-N synthesizer in a 0.25mum BiCMOS process and achieves 50dB IRR over the entire signal bandwidth at 200kHz IF\",\"PeriodicalId\":166617,\"journal\":{\"name\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2006.1696249\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2006.1696249","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
摘要
用于GSM/EDGE低中频接收器的宽带图像抑制电路包括参考信号源和补偿I/Q增益、相位和频率响应不匹配的数字校正电路。该芯片集成了LNA、混频器、PGAs、lpf和分数n合成器,采用0.25 μ m BiCMOS工艺,在200kHz中频下,整个信号带宽达到50dB的IRR
Wideband Image-Rejection Circuit for Low-IF Receivers
A wideband image-rejection circuit for GSM/EDGE low-IF receivers includes a reference signal source and digital correction circuit that compensate I/Q gain, phase, and frequency response mismatch. The chip integrates an LNA, mixers, PGAs, LPFs, and fractional-N synthesizer in a 0.25mum BiCMOS process and achieves 50dB IRR over the entire signal bandwidth at 200kHz IF