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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers最新文献

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A CMOS Temperature-to-Frequency Converter with an Inaccuracy of 0.5/spl deg/C (3 /spl sigma/) from -40 to 105/spl deg/C 一种CMOS温度-频率转换器，误差为0.5/spl度/C (3 /spl sigma/)，范围为-40至105/spl度/C
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696159
K. Makinwa, Martijn F. Snoeij
{"title":"A CMOS Temperature-to-Frequency Converter with an Inaccuracy of 0.5/spl deg/C (3 /spl sigma/) from -40 to 105/spl deg/C","authors":"K. Makinwa, Martijn F. Snoeij","doi":"10.1109/ISSCC.2006.1696159","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696159","url":null,"abstract":"A temperature-to-frequency converter implemented in a standard CMOS process only requires a low-cost batch calibration. Its output frequency is determined by the process-independent (but temperature-dependent) thermal diffusivity of bulk silicon. The converter's inaccuracy is less than plusmn0.5degC (3sigma) over the extended industrial temperature range from -40 to 105degC","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122859625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning 一个0.5至2.5GHz锁相环与全差分电源调节调谐
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696305
M. Brownlee, P. Hanumolu, K. Mayaram, U. Moon
{"title":"A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning","authors":"M. Brownlee, P. Hanumolu, K. Mayaram, U. Moon","doi":"10.1109/ISSCC.2006.1696305","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696305","url":null,"abstract":"A PLL uses a fully differential supply-regulated tuning scheme to combat power-supply noise. The charge pump uses a resistor to set the current and reduce the flicker noise corner. Fabricated in a 0.18mum CMOS process, the PLL area is 0.15mm2. Operating at 2.4GHz, it has 3.29psrms jitter, a frequency range of 0.5 to 2.5GHz, and draws 14mA from a 1.8V supply","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122925923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control 具有TX上升/下降时间控制的四路6Gb/s多速率CMOS收发器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696053
Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim
{"title":"A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control","authors":"Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim","doi":"10.1109/ISSCC.2006.1696053","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696053","url":null,"abstract":"A multi-rate transceiver incorporating TX slew control with >2times range, PLL with <0.5times loop-filter area using capacitance multiplication, and DeltaSigmaZ-SSCG having 11.7dB peak reduction is designed in 0.13mum CMOS. Occupying 2.33mm2 with TX operable up to 8.5Gb/s, the quad transceiver consumes 386mW from 1.2V supply and has a BER<10-14 at 6Gb/s over an 8m cable with 22dB loss","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125388137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A Bandpass /spl Delta//spl Sigma/ RF-DAC with Embedded FIR Reconstruction Filter 带通/spl Delta//spl Sigma/ rf dac，内置FIR重构滤波器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696300
Shahin Mehdizad Taleie, T. Copani, B. Bakkaloglu, S. Kiaei
{"title":"A Bandpass /spl Delta//spl Sigma/ RF-DAC with Embedded FIR Reconstruction Filter","authors":"Shahin Mehdizad Taleie, T. Copani, B. Bakkaloglu, S. Kiaei","doi":"10.1109/ISSCC.2006.1696300","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696300","url":null,"abstract":"A 1b bandpass DeltaSigma DAC followed by a current steering FIR reconstruction filter and an embedded up-conversion mixer is presented. The RF DAC is implemented in 0.25mum digital CMOS, can be used in low-power digital-IF transmitters and eliminates the need for a transimpedance stage and a separate mixer. The RF DAC draws 49mA from a 2.5V supply, achieving -64.7dBc IM3 at 1.03GHz with an SFDR of 72dB in a 15MHz bandwidth","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129361275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers 用于数字电视接收机的80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696049
Y. Fujimoto, Y. Kanazawa, Pascal Lo Ré, M. Miyamoto
{"title":"An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers","authors":"Y. Fujimoto, Y. Kanazawa, Pascal Lo Ré, M. Miyamoto","doi":"10.1109/ISSCC.2006.1696049","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696049","url":null,"abstract":"A 4th-order SC DeltaSigma modulator with a 4b quantizer is designed for a low-power direct-conversion receiver SoC for Japanese ISDB-T and European DVB-T. It achieves a 76.3/70.1dB SNDR over a 3.2/4MHz bandwidth with a clock frequency of 80/100MHz. The 1.7mm2 chip, fabricated in a 0.18mum CMOS process draws 13.2/19.1mA from a 1.8V supply. It has a FOM of 0.7/1.64pJ/conversion","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129391284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25/spl mu/m CMOS 630MHz直接数字频率合成器，90dBc SFDR, 0.25/spl mu/m CMOS
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696139
D. Caro, N. Petra, A. Strollo
{"title":"A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25/spl mu/m CMOS","authors":"D. Caro, N. Petra, A. Strollo","doi":"10.1109/ISSCC.2006.1696139","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696139","url":null,"abstract":"Multipartite table methods are used in the implementation of a direct digital frequency synthesizer. Two quadrature 13b outputs are produced with a SFDR >90dB and a frequency resolution of 0.15Hz at a 630MHz clock frequency. The 0.25mum CMOS chip occupies 0.063mm2 and dissipates 76mW from a 2.5V supply at 630MHz","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129484751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications 1.83ps分辨率CMOS动态任意时序发生器，适用于>4GHz ATE应用
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696272
T. Okayasu, M. Suda, Kazuhiro Yamamoto, Shusuke Kantake, Satoshi Sudou, D. Watanabe
{"title":"1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications","authors":"T. Okayasu, M. Suda, Kazuhiro Yamamoto, Shusuke Kantake, Satoshi Sudou, D. Watanabe","doi":"10.1109/ISSCC.2006.1696272","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696272","url":null,"abstract":"A high-speed high-precision dynamic arbitrary timing generator, fabricated in a 0.18mum CMOS process, for >4GHz ATE applications is demonstrated. It exhibits a maximum operating frequency of 1.066 and 4.266GHz (multiplexed mode), a timing resolution of 1.83ps, an INL of <plusmn4ps excluding the calibration RAM, and a random jitter of <0.7psrms","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128020291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes 一个16Mb的MRAM，带有分叉布线方案和突发模式
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696080
Y. Iwata, K. Tsuchida, T. Inaba, Yui Shimizu, R. Takizawa, Y. Ueda, T. Sugibayashi, Y. Asao, T. Kajiyama, K. Hosotani, S. Ikegawa, T. Kai, M. Nakayama, S. Tahara, H. Yoda
{"title":"A 16Mb MRAM with FORK Wiring Scheme and Burst Modes","authors":"Y. Iwata, K. Tsuchida, T. Inaba, Yui Shimizu, R. Takizawa, Y. Ueda, T. Sugibayashi, Y. Asao, T. Kajiyama, K. Hosotani, S. Ikegawa, T. Kai, M. Nakayama, S. Tahara, H. Yoda","doi":"10.1109/ISSCC.2006.1696080","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696080","url":null,"abstract":"A 16Mb MRAM based on 0.13mum CMOS and 0.24mum MRAM process achieves a 34ns asynchronous access and 100MHz synchronous operation, compatible with pseudo-SRAM for mobile applications. By implementation of FORK wiring scheme, the cell efficiency is raised to 39.9% and the disturb robustness of half-selection state is improved","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129165114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 15mW 0.2mm/sup 2/ 50MS/s ADC with wide input range 具有宽输入范围的15mW 0.2mm/sup / 50MS/s ADC
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696124
Hee-Cheol Choi, Ju-Wha Kim, Sang-Min Yoo, Kang-Jin Lee, Tae-Hwan Oh, MinGu Seo, Jae-Whui Kim
{"title":"A 15mW 0.2mm/sup 2/ 50MS/s ADC with wide input range","authors":"Hee-Cheol Choi, Ju-Wha Kim, Sang-Min Yoo, Kang-Jin Lee, Tae-Hwan Oh, MinGu Seo, Jae-Whui Kim","doi":"10.1109/ISSCC.2006.1696124","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696124","url":null,"abstract":"A 10b 50MS/s pipelined ADC, implemented in a 0.13mum CMOS process, consumes of 15mW and occupies an active die area of 0.2mm2 . In the prototype ADC, a high-to-low analog level-shifting SHA is proposed to deal with a wide input range of 2VPP differential. A PVT-insensitive bias generator is employed for low voltage operation. The measured DNL and INL are plusmn0.17LSB and plusmn0.16LSB, respectively","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130793547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology 采用0.35/spl mu/m FeRAM技术的无源UHF RFID标签LSI，具有36.6%效率的cmos整流器和电流模式解调器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696166
H. Nakamoto, D. Yamazaki, T. Yamamoto, H. Kurata, S. Yamada, K. Mukaida, T. Ninomiya, T. Ohkawa, S. Masui, K. Gotoh
{"title":"A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology","authors":"H. Nakamoto, D. Yamazaki, T. Yamamoto, H. Kurata, S. Yamada, K. Mukaida, T. Ninomiya, T. Ohkawa, S. Masui, K. Gotoh","doi":"10.1109/ISSCC.2006.1696166","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696166","url":null,"abstract":"A passive UHF RFID tag LSI in 0.35mum CMOS with 2kb FeRAM enables the 2.9-times higher 32b read-and-write throughput over an EEPROM-based tag. A CMOS full-wave rectifier improves the power efficiency from 16.6% up to 36.6% by lossless internal Vth cancellation and mirror stack architecture. A current-mode ASK demodulator converts the 15% power modulation into linear current signal over a 27dB dynamic range of the incoming power","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"56 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116560088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 87
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