用于数字电视接收机的80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696049

Y. Fujimoto, Y. Kanazawa, Pascal Lo Ré, M. Miyamoto

{"title":"用于数字电视接收机的80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC","authors":"Y. Fujimoto, Y. Kanazawa, Pascal Lo Ré, M. Miyamoto","doi":"10.1109/ISSCC.2006.1696049","DOIUrl":null,"url":null,"abstract":"A 4th-order SC DeltaSigma modulator with a 4b quantizer is designed for a low-power direct-conversion receiver SoC for Japanese ISDB-T and European DVB-T. It achieves a 76.3/70.1dB SNDR over a 3.2/4MHz bandwidth with a clock frequency of 80/100MHz. The 1.7mm2 chip, fabricated in a 0.18mum CMOS process draws 13.2/19.1mA from a 1.8V supply. It has a FOM of 0.7/1.64pJ/conversion","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers\",\"authors\":\"Y. Fujimoto, Y. Kanazawa, Pascal Lo Ré, M. Miyamoto\",\"doi\":\"10.1109/ISSCC.2006.1696049\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 4th-order SC DeltaSigma modulator with a 4b quantizer is designed for a low-power direct-conversion receiver SoC for Japanese ISDB-T and European DVB-T. It achieves a 76.3/70.1dB SNDR over a 3.2/4MHz bandwidth with a clock frequency of 80/100MHz. The 1.7mm2 chip, fabricated in a 0.18mum CMOS process draws 13.2/19.1mA from a 1.8V supply. It has a FOM of 0.7/1.64pJ/conversion\",\"PeriodicalId\":166617,\"journal\":{\"name\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2006.1696049\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2006.1696049","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 19

摘要

针对日本ISDB-T和欧洲DVB-T的低功耗直接转换接收机SoC，设计了一种带4b量化器的4阶SC DeltaSigma调制器。时钟频率为80/100MHz，在3.2/4MHz带宽上实现76.3/70.1dB SNDR。该1.7mm2芯片采用0.18 μ m CMOS工艺制造，从1.8V电源中吸收13.2/19.1mA。它的FOM为0.7/1.64pJ/转换

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An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers

A 4th-order SC DeltaSigma modulator with a 4b quantizer is designed for a low-power direct-conversion receiver SoC for Japanese ISDB-T and European DVB-T. It achieves a 76.3/70.1dB SNDR over a 3.2/4MHz bandwidth with a clock frequency of 80/100MHz. The 1.7mm2 chip, fabricated in a 0.18mum CMOS process draws 13.2/19.1mA from a 1.8V supply. It has a FOM of 0.7/1.64pJ/conversion

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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