具有TX上升/下降时间控制的四路6Gb/s多速率CMOS收发器

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696053

Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim

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引用次数: 15

摘要

采用0.13 μ m CMOS设计了一种多速率收发器，该收发器具有>2倍范围的TX转换控制，使用电容倍增的环滤波面积<0.5倍的锁相环，以及峰值降低11.7dB的DeltaSigmaZ-SSCG。占地2.33mm2, TX可高达8.5Gb/s，四路收发器在1.2V电源下消耗386mW，在6Gb/s下，在8m电缆上的误码率<10-14，损耗为22dB

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A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control

A multi-rate transceiver incorporating TX slew control with >2times range, PLL with <0.5times loop-filter area using capacitance multiplication, and DeltaSigmaZ-SSCG having 11.7dB peak reduction is designed in 0.13mum CMOS. Occupying 2.33mm2 with TX operable up to 8.5Gb/s, the quad transceiver consumes 386mW from 1.2V supply and has a BER<10-14 at 6Gb/s over an 8m cable with 22dB loss

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来源期刊

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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