An 80/100MS/s 76.3/70.1dB SNDR /spl Delta//spl Sigma/ ADC for Digital TV Receivers

Abstract

A 4th-order SC DeltaSigma modulator with a 4b quantizer is designed for a low-power direct-conversion receiver SoC for Japanese ISDB-T and European DVB-T. It achieves a 76.3/70.1dB SNDR over a 3.2/4MHz bandwidth with a clock frequency of 80/100MHz. The 1.7mm2 chip, fabricated in a 0.18mum CMOS process draws 13.2/19.1mA from a 1.8V supply. It has a FOM of 0.7/1.64pJ/conversion