630MHz直接数字频率合成器，90dBc SFDR, 0.25/spl mu/m CMOS

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696139

D. Caro, N. Petra, A. Strollo

{"title":"630MHz直接数字频率合成器，90dBc SFDR, 0.25/spl mu/m CMOS","authors":"D. Caro, N. Petra, A. Strollo","doi":"10.1109/ISSCC.2006.1696139","DOIUrl":null,"url":null,"abstract":"Multipartite table methods are used in the implementation of a direct digital frequency synthesizer. Two quadrature 13b outputs are produced with a SFDR >90dB and a frequency resolution of 0.15Hz at a 630MHz clock frequency. The 0.25mum CMOS chip occupies 0.063mm2 and dissipates 76mW from a 2.5V supply at 630MHz","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25/spl mu/m CMOS\",\"authors\":\"D. Caro, N. Petra, A. Strollo\",\"doi\":\"10.1109/ISSCC.2006.1696139\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multipartite table methods are used in the implementation of a direct digital frequency synthesizer. Two quadrature 13b outputs are produced with a SFDR >90dB and a frequency resolution of 0.15Hz at a 630MHz clock frequency. The 0.25mum CMOS chip occupies 0.063mm2 and dissipates 76mW from a 2.5V supply at 630MHz\",\"PeriodicalId\":166617,\"journal\":{\"name\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2006.1696139\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2006.1696139","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

多部表方法用于直接数字频率合成器的实现。两个正交13b输出，SFDR >90dB，频率分辨率为0.15Hz，时钟频率为630MHz。0.25 μ m CMOS芯片占用0.063mm2，在630MHz时从2.5V电源消耗76mW

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A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25/spl mu/m CMOS

Multipartite table methods are used in the implementation of a direct digital frequency synthesizer. Two quadrature 13b outputs are produced with a SFDR >90dB and a frequency resolution of 0.15Hz at a 630MHz clock frequency. The 0.25mum CMOS chip occupies 0.063mm2 and dissipates 76mW from a 2.5V supply at 630MHz

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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