A 15mW 0.2mm/sup 2/ 50MS/s ADC with wide input range

Abstract

A 10b 50MS/s pipelined ADC, implemented in a 0.13mum CMOS process, consumes of 15mW and occupies an active die area of 0.2mm2 . In the prototype ADC, a high-to-low analog level-shifting SHA is proposed to deal with a wide input range of 2VPP differential. A PVT-insensitive bias generator is employed for low voltage operation. The measured DNL and INL are plusmn0.17LSB and plusmn0.16LSB, respectively