具有宽输入范围的15mW 0.2mm/sup / 50MS/s ADC

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696124

Hee-Cheol Choi, Ju-Wha Kim, Sang-Min Yoo, Kang-Jin Lee, Tae-Hwan Oh, MinGu Seo, Jae-Whui Kim

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引用次数: 12

摘要

采用0.13 μ m CMOS工艺实现的10b 50MS/s流水线ADC，功耗为15mW，占据0.2mm2的有效芯片面积。在原型ADC中，提出了一个高低模拟移电平SHA来处理2VPP差分的宽输入范围。低压工作采用pvt不敏感偏置发生器。测得的DNL和INL分别为±0.17 lsb和±0.16 lsb

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A 15mW 0.2mm/sup 2/ 50MS/s ADC with wide input range

A 10b 50MS/s pipelined ADC, implemented in a 0.13mum CMOS process, consumes of 15mW and occupies an active die area of 0.2mm2 . In the prototype ADC, a high-to-low analog level-shifting SHA is proposed to deal with a wide input range of 2VPP differential. A PVT-insensitive bias generator is employed for low voltage operation. The measured DNL and INL are plusmn0.17LSB and plusmn0.16LSB, respectively

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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