Y. Iwata, K. Tsuchida, T. Inaba, Yui Shimizu, R. Takizawa, Y. Ueda, T. Sugibayashi, Y. Asao, T. Kajiyama, K. Hosotani, S. Ikegawa, T. Kai, M. Nakayama, S. Tahara, H. Yoda
{"title":"A 16Mb MRAM with FORK Wiring Scheme and Burst Modes","authors":"Y. Iwata, K. Tsuchida, T. Inaba, Yui Shimizu, R. Takizawa, Y. Ueda, T. Sugibayashi, Y. Asao, T. Kajiyama, K. Hosotani, S. Ikegawa, T. Kai, M. Nakayama, S. Tahara, H. Yoda","doi":"10.1109/ISSCC.2006.1696080","DOIUrl":null,"url":null,"abstract":"A 16Mb MRAM based on 0.13mum CMOS and 0.24mum MRAM process achieves a 34ns asynchronous access and 100MHz synchronous operation, compatible with pseudo-SRAM for mobile applications. By implementation of FORK wiring scheme, the cell efficiency is raised to 39.9% and the disturb robustness of half-selection state is improved","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2006.1696080","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
A 16Mb MRAM based on 0.13mum CMOS and 0.24mum MRAM process achieves a 34ns asynchronous access and 100MHz synchronous operation, compatible with pseudo-SRAM for mobile applications. By implementation of FORK wiring scheme, the cell efficiency is raised to 39.9% and the disturb robustness of half-selection state is improved