一种用于40GHz锁相环的80nm CMOS动态与静态组合分频器

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696310

G. V. Büren, C. Kromer, F. Ellinger, A. Huber, M. Schmatz, H. Jäckel

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引用次数: 21

摘要

在信号幅度为0.5Vpp的情况下，输入频率为31至41 GHz的除以4电路工作。该电路由一个动态分频器和一个静态分频器组成。动态分频器和静态分频器分别从1.1V电源消耗2mA和1mA

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A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS

A divide-by-4 circuit operates for input frequencies from 31 to 41 GHz at signal amplitudes "0.5Vpp. The circuit consists of a dynamic followed by a static frequency divider. The dynamic and static frequency dividers consume 2mA and 1mA, respectively, from a 1.1V supply

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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