一个120Mvertices/s的多线程VLIW顶点处理器，用于移动多媒体应用

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696215

Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, L. Kim

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引用次数: 22

摘要

一个具有浮点4线程和4问题VLIW架构和TnL顶点缓存的3D顶点处理器在0.18m m CMOS工艺中实现，用于移动多媒体应用。所提出的架构有效地降低了总能耗，并在100MHz工作时使用157mW以2.5GFLOPS数据路径实现120Mvertices/s

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A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications

A 3D vertex processor with a floating-point 4-threaded and 4-issue VLIW architecture and a TnL vertex cache is implemented for mobile multimedia applications in a 0.18mum 4M CMOS process. The proposed architecture efficiently reduces the total energy consumption and achieves 120Mvertices/s with a 2.5GFLOPS datapath using 157mW when operating at 100MHz

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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