A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696302

Kok Lim Chan, I. Galton

引用次数: 38

Abstract

A 14b 100MS/s Nyquist-rate DAC using a segmented dynamic-element-matching technique involving all the DAC elements is demonstrated. The DAC is implemented in a 0.18mum CMOS process and worst-case SFDRs across Nyquist bands are 74.4dB and 78.9dB for sample-rates of 100MS/s and 70Ms/s, respectively

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具有完全分段动态元件匹配的14b 100MS/s DAC

采用分段动态元件匹配技术的14b 100MS/s奈奎斯特速率DAC涉及所有DAC元件的演示。该DAC采用0.18 μ m CMOS工艺实现，采样率为100MS/s和70Ms/s时，Nyquist频带的最坏情况sfdr分别为74.4dB和78.9dB

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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