采用动态列FPN降阶的CMOS列级ADC成像仪

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696260

Martijn F. Snoeij, A. Theuwissen, K. Makinwa, J. Huijsing

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引用次数: 6

摘要

具有列级ADC的CMOS成像仪采用动态列FPN缩减技术。这种技术需要每列5个额外的开关，并且在芯片级上的数字开销最小，同时减少了列FPN的感知效果。测量表明，该原型使柱FPN为±0.67%几乎不可见

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A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction

A CMOS imager with a column-level ADC uses a dynamic column FPN reduction technique. This technique requires 5 extra switches per column and minimal digital overhead at the chip level while reducing the perceptual effect of column FPN. Measurements show that the prototype makes a column FPN of plusmn0.67% nearly invisible

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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