基于lms的DAC增益校准的1.8GHz杂散抵消分数n频率合成器

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696250

M. Gupta, B. Song

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引用次数: 71

摘要

1.8GHz宽带分数n合成器采用自适应LMS杂散相关技术校准的消噪DAC实现整数n锁相环的相位噪声。其带内噪声和集成相位噪声分别为-98dBc/Hz和0.8°。0.18 μ m CMOS芯片占地2mm2, 1.8V时功耗29mW

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A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration

A 1.8GHz wideband fractional-N synthesizer achieves the phase noise of an integer-N PLL using a noise-cancellation DAC calibrated with an adaptive LMS spur correlation technique. It exhibits in-band and integrated phase noises of -98dBc/Hz and 0.8deg, respectively. The chip in 0.18mum CMOS occupies 2mm2, and consumes 29mW at 1.8V

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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