1.1ghz电荷恢复逻辑

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696205

V. Sathe, Juang-Ying Chueh, Marios Papaefthymio

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引用次数: 13

摘要

采用0.13 μ m CMOS工艺，采用片上时钟发生器和集成电感实现了ghz级动态电荷恢复逻辑。芯片操作在时钟频率高达1.3GHz的情况下进行了验证。在其固有频率下，该设计每循环回收总电路能量的60%

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A 1.1ghz charge-recovery logic

A GHz-class dynamic charge-recovery logic is implemented with an on-chip clock generator and integrated inductor in a 0.13mum CMOS process. The chip operation is verified at clock frequencies up to 1.3GHz. At its natural frequency, the design recovers 60% of total circuit energy every cycle

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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