用于POWER6处理器的4GHz+低延迟定点和二进制浮点执行单元

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696229

B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. Chan, D. Webber, Vaden Vaden, A. Goyal

{"title":"用于POWER6处理器的4GHz+低延迟定点和二进制浮点执行单元","authors":"B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. Chan, D. Webber, Vaden Vaden, A. Goyal","doi":"10.1109/ISSCC.2006.1696229","DOIUrl":null,"url":null,"abstract":"A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor\",\"authors\":\"B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. Chan, D. Webber, Vaden Vaden, A. Goyal\",\"doi\":\"10.1109/ISSCC.2006.1696229\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases\",\"PeriodicalId\":166617,\"journal\":{\"name\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"volume\":\"86 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2006.1696229\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2006.1696229","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 20

摘要

1管道级，低延迟，13 FO4, 64b定点执行单元，在65nm SOI CMOS工艺中实现，允许背靠背执行数据相关的加法，减法，比较，移位，旋转和逻辑操作。在大多数情况下，一个7管道级，91 FO4，双精度浮点单元允许在6个周期后转发相关结果

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4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor

A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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